coreboot-gerrit February 2021

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Change in coreboot[master]: mb/google/guybrush: stubs to configure GPIOs
by Angel Pons (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Martin Roth, Mathew King. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49954 ) Change subject: mb/google/guybrush: stubs to configure GPIOs ...................................................................... Patch Set 10: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49954/comment/07ccbd3b_f4170cae PS10, Line 7: stubs to configure GPIOs Add stubs to configure GPIOs -- To view, visit https://review.coreboot.org/c/coreboot/+/49954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c Gerrit-Change-Number: 49954 Gerrit-PatchSet: 10 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 10:21:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Create kracko variant
by Tony Huang (Code Review) 03 Feb '21

03 Feb '21

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50255 ) Change subject: mb/google/dedede: Create kracko variant ...................................................................... mb/google/dedede: Create kracko variant Create the kracko variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:178092096 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_KRACKO Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/kracko/include/variant/ec.h A src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h A src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc A src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/kracko/overridetree.cb 8 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/50255/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 6928002..833a674 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -101,6 +101,7 @@ default "Sasuke" if BOARD_GOOGLE_SASUKE default "Storo" if BOARD_GOOGLE_STORO default "Sasukette" if BOARD_GOOGLE_SASUKETTE + default "Kracko" if BOARD_GOOGLE_KRACKO config MAX_CPUS int @@ -136,5 +137,6 @@ default "sasuke" if BOARD_GOOGLE_SASUKE default "storo" if BOARD_GOOGLE_STORO default "sasukette" if BOARD_GOOGLE_SASUKETTE + default "kracko" if BOARD_GOOGLE_KRACKO endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 97b90c2..a1d129e 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -104,3 +104,9 @@ bool "-> Sasukette" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_KRACKO + bool "-> Kracko" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h b/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc b/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc new file mode 100644 index 0000000..f6282bf --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt new file mode 100644 index 0000000..856d016 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt new file mode 100644 index 0000000..26c06b6 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt @@ -0,0 +1,3 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb new file mode 100644 index 0000000..8620882 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | | + #| I2C4 | Audio | + #| I2C5 | P-Sensor | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.3 off end #I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/50255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed Gerrit-Change-Number: 50255 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
by Subrata Banik (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50254 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h ...................................................................... Patch Set 2: (1 comment) File src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h: https://review.coreboot.org/c/coreboot/+/50254/comment/be427833_c914e7ff PS1, Line 27: MAX_TRACE_CACHE_TYPE > MAX_TRACE_CACHE_TYPE already defined here? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Gerrit-Change-Number: 50254 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 10:19:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
by Subrata Banik (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50254 to look at the new patch set (#2). Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 10 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50254/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Gerrit-Change-Number: 50254 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Codify some guidelines for headers and chain-including
by HAOUAS Elyes (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Martin Roth, Julius Werner. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50247 ) Change subject: Documentation: Codify some guidelines for headers and chain-including ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > Thanks! We probably have to collect the list of exceptions in a separate file and link it here. here is what I've tried to list: include/cbfs.h: commonlib/cbfs.h: commonlib/bsd/cbfs_private.h: commonlib/bsd/cb_err.h commonlib/bsd/cbfs_serialized.h include/gpio.h: soc/gpio.h include/types.h: commonlib/bsd/cb_err.h stdbool.h stdint.h stddef.h include/gpio.h: soc/gpio.h include/device/mmio.h: arch/mmio.h include/device/pci_ops.h: arch/pci_ops.h: device/pci_mmio_cfg.h arch/pci_io_cfg.h: arch/io.h -- To view, visit https://review.coreboot.org/c/coreboot/+/50247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0 Gerrit-Change-Number: 50247 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 10:09:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
by Angel Pons (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50254 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h ...................................................................... Patch Set 1: (2 comments) File src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h: https://review.coreboot.org/c/coreboot/+/50254/comment/fa1f5a27_4a4130a4 PS1, Line 27: MAX_TRACE_CACHE_TYPE MAX_TRACE_CACHE_TYPE already defined here? https://review.coreboot.org/c/coreboot/+/50254/comment/2aa7e0de_44b77a6a PS1, Line 156: MAX_TRACE_REGION Looks like nothing currently uses this definition -- To view, visit https://review.coreboot.org/c/coreboot/+/50254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Gerrit-Change-Number: 50254 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 09:44:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
by Subrata Banik (Code Review) 03 Feb '21

03 Feb '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50254 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50254/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h index 816ce06..0b65eda 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h @@ -4,7 +4,7 @@ data hobs. @copyright - Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR> + Copyright (c) 1999 - 2021, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -153,6 +153,9 @@ #define MAX_PROFILE_NUM 4 // number of memory profiles supported #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + // // DIMM timings // -- To view, visit https://review.coreboot.org/c/coreboot/+/50254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Gerrit-Change-Number: 50254 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Modify USB 3.0 PHY parameters for galith
by Frank Chu (Code Review) 03 Feb '21

03 Feb '21

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50253 ) Change subject: mb/google/dedede: Modify USB 3.0 PHY parameters for galith ...................................................................... mb/google/dedede: Modify USB 3.0 PHY parameters for galith Modify USB 3.0 PHY parameters for improve usb eye diagram. USB 3.0 TypeC port2: .tx_de_emp = 0x20, .tx_downscale_amp = 0x00, BUG=b:179224587 BRANCH=dedede TEST=cros build-ap --debug -b dedede --fw-name galtic Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I66dc9b5a7280bfd42592b07f160f48797613fdd6 --- M src/mainboard/google/dedede/variants/galtic/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/50253/1 diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index 9ed1dd0..f3854e6 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -57,6 +57,14 @@ # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + #These settings improve the USB eye diagram + #USB3 Port2 + register "usb3_ports[1]" = "{ + .enable = 1, + .tx_de_emp = 0x20, + .tx_downscale_amp = 0x00, + }" + device domain 0 on device pci 14.0 on chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/50253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66dc9b5a7280bfd42592b07f160f48797613fdd6 Gerrit-Change-Number: 50253 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ids/intel: Add missing CFL-S GT1 IGD IDs
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50089 ) Change subject: pci_ids/intel: Add missing CFL-S GT1 IGD IDs ...................................................................... pci_ids/intel: Add missing CFL-S GT1 IGD IDs Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50089 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Timofey Komarov <happycorsair(a)yandex.ru> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Timofey Komarov: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6f48d15..896183f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3713,6 +3713,8 @@ #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b #define PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2 0x3e94 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT1_1 0x3e90 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT1_2 0x3e93 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_1 0x3e92 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 011b8ea..9c393e5 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -122,6 +122,8 @@ { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, "Coffeelake-S GT1" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, "Coffeelake-S GT1" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 25422ea..ca96f35 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -221,6 +221,8 @@ PCI_DEVICE_ID_INTEL_SKL_GT4E_SWSTM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, + PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, -- To view, visit https://review.coreboot.org/c/coreboot/+/50089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b Gerrit-Change-Number: 50089 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: pci_ids/intel: Correct 0x3e96, it's a CFL-S part
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50088 ) Change subject: pci_ids/intel: Correct 0x3e96, it's a CFL-S part ...................................................................... pci_ids/intel: Correct 0x3e96, it's a CFL-S part Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Timofey Komarov <happycorsair(a)yandex.ru> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Timofey Komarov: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 62524a3..6f48d15 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3717,7 +3717,7 @@ #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_4 0x3e91 -#define PCI_DEVICE_ID_INTEL_CFL_U_GT2 0x3e96 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_5 0x3e96 #define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 #define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 87b4be7..011b8ea 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -126,7 +126,7 @@ { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, "Coffeelake-S GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_U_GT2, "Coffeelake-U GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 7150bab..25422ea 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -225,7 +225,7 @@ PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, - PCI_DEVICE_ID_INTEL_CFL_U_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, -- To view, visit https://review.coreboot.org/c/coreboot/+/50088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Gerrit-Change-Number: 50088 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021