coreboot-gerrit February 2021

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
by Subrata Banik (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50254 to look at the new patch set (#2). Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 10 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50254/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Gerrit-Change-Number: 50254 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Codify some guidelines for headers and chain-including
by HAOUAS Elyes (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Martin Roth, Julius Werner. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50247 ) Change subject: Documentation: Codify some guidelines for headers and chain-including ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > Thanks! We probably have to collect the list of exceptions in a separate file and link it here. here is what I've tried to list: include/cbfs.h: commonlib/cbfs.h: commonlib/bsd/cbfs_private.h: commonlib/bsd/cb_err.h commonlib/bsd/cbfs_serialized.h include/gpio.h: soc/gpio.h include/types.h: commonlib/bsd/cb_err.h stdbool.h stdint.h stddef.h include/gpio.h: soc/gpio.h include/device/mmio.h: arch/mmio.h include/device/pci_ops.h: arch/pci_ops.h: device/pci_mmio_cfg.h arch/pci_io_cfg.h: arch/io.h -- To view, visit https://review.coreboot.org/c/coreboot/+/50247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0 Gerrit-Change-Number: 50247 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 10:09:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
by Angel Pons (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50254 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h ...................................................................... Patch Set 1: (2 comments) File src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h: https://review.coreboot.org/c/coreboot/+/50254/comment/fa1f5a27_4a4130a4 PS1, Line 27: MAX_TRACE_CACHE_TYPE MAX_TRACE_CACHE_TYPE already defined here? https://review.coreboot.org/c/coreboot/+/50254/comment/2aa7e0de_44b77a6a PS1, Line 156: MAX_TRACE_REGION Looks like nothing currently uses this definition -- To view, visit https://review.coreboot.org/c/coreboot/+/50254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Gerrit-Change-Number: 50254 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 09:44:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
by Subrata Banik (Code Review) 03 Feb '21

03 Feb '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50254 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50254/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h index 816ce06..0b65eda 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h @@ -4,7 +4,7 @@ data hobs. @copyright - Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR> + Copyright (c) 1999 - 2021, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -153,6 +153,9 @@ #define MAX_PROFILE_NUM 4 // number of memory profiles supported #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + // // DIMM timings // -- To view, visit https://review.coreboot.org/c/coreboot/+/50254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Gerrit-Change-Number: 50254 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Modify USB 3.0 PHY parameters for galith
by Frank Chu (Code Review) 03 Feb '21

03 Feb '21

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50253 ) Change subject: mb/google/dedede: Modify USB 3.0 PHY parameters for galith ...................................................................... mb/google/dedede: Modify USB 3.0 PHY parameters for galith Modify USB 3.0 PHY parameters for improve usb eye diagram. USB 3.0 TypeC port2: .tx_de_emp = 0x20, .tx_downscale_amp = 0x00, BUG=b:179224587 BRANCH=dedede TEST=cros build-ap --debug -b dedede --fw-name galtic Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I66dc9b5a7280bfd42592b07f160f48797613fdd6 --- M src/mainboard/google/dedede/variants/galtic/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/50253/1 diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index 9ed1dd0..f3854e6 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -57,6 +57,14 @@ # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + #These settings improve the USB eye diagram + #USB3 Port2 + register "usb3_ports[1]" = "{ + .enable = 1, + .tx_de_emp = 0x20, + .tx_downscale_amp = 0x00, + }" + device domain 0 on device pci 14.0 on chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/50253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66dc9b5a7280bfd42592b07f160f48797613fdd6 Gerrit-Change-Number: 50253 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ids/intel: Add missing CFL-S GT1 IGD IDs
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50089 ) Change subject: pci_ids/intel: Add missing CFL-S GT1 IGD IDs ...................................................................... pci_ids/intel: Add missing CFL-S GT1 IGD IDs Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50089 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Timofey Komarov <happycorsair(a)yandex.ru> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Timofey Komarov: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6f48d15..896183f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3713,6 +3713,8 @@ #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b #define PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2 0x3e94 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT1_1 0x3e90 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT1_2 0x3e93 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_1 0x3e92 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 011b8ea..9c393e5 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -122,6 +122,8 @@ { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, "Coffeelake-S GT1" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, "Coffeelake-S GT1" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 25422ea..ca96f35 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -221,6 +221,8 @@ PCI_DEVICE_ID_INTEL_SKL_GT4E_SWSTM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, + PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, -- To view, visit https://review.coreboot.org/c/coreboot/+/50089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b Gerrit-Change-Number: 50089 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: pci_ids/intel: Correct 0x3e96, it's a CFL-S part
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50088 ) Change subject: pci_ids/intel: Correct 0x3e96, it's a CFL-S part ...................................................................... pci_ids/intel: Correct 0x3e96, it's a CFL-S part Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Timofey Komarov <happycorsair(a)yandex.ru> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Timofey Komarov: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 62524a3..6f48d15 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3717,7 +3717,7 @@ #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_4 0x3e91 -#define PCI_DEVICE_ID_INTEL_CFL_U_GT2 0x3e96 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_5 0x3e96 #define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 #define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 87b4be7..011b8ea 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -126,7 +126,7 @@ { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, "Coffeelake-S GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_U_GT2, "Coffeelake-U GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 7150bab..25422ea 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -225,7 +225,7 @@ PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, - PCI_DEVICE_ID_INTEL_CFL_U_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, -- To view, visit https://review.coreboot.org/c/coreboot/+/50088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Gerrit-Change-Number: 50088 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor
by Kyösti Mälkki (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50252 ) Change subject: soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor ...................................................................... soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor Change-Id: Ie3feee0448175db2b6ed4e8e37d92de3af9be371 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/gma.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/50252/1 diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 45d1833..b6ce426 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -515,12 +515,8 @@ /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { -#if CONFIG(CHROMEOS) - if (display_init_required()) + if (!CONFIG(CHROMEOS) || display_init_required()) mdelay(CONFIG_PRE_GRAPHICS_DELAY); -#else - mdelay(CONFIG_PRE_GRAPHICS_DELAY); -#endif } /* Early init steps */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3feee0448175db2b6ed4e8e37d92de3af9be371 Gerrit-Change-Number: 50252 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ids/intel: Correct 0x3e96, it's a CFL-S part
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Nico Huber, Christian Walter, Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50088 ) Change subject: pci_ids/intel: Correct 0x3e96, it's a CFL-S part ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Gerrit-Change-Number: 50088 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 08:57:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src: Remove unused <boardid.h>
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50183 ) Change subject: src: Remove unused <boardid.h> ...................................................................... src: Remove unused <boardid.h> Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/drallion/ramstage.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/gale/cdp.c M src/mainboard/google/gale/mainboard.c M src/mainboard/google/hatch/variants/palkia/memory.c M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/nyan_big/pmic.c M src/mainboard/google/nyan_blaze/pmic.c M src/mainboard/google/octopus/variants/casta/gpio.c M src/mainboard/google/octopus/variants/dood/variant.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/lick/gpio.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/berknip/gpio.c M src/mainboard/google/zork/variants/dalboz/gpio.c M src/mainboard/google/zork/variants/dirinboz/gpio.c M src/mainboard/google/zork/variants/ezkinil/gpio.c M src/mainboard/google/zork/variants/gumboz/gpio.c M src/mainboard/google/zork/variants/morphius/gpio.c M src/mainboard/google/zork/variants/shuboz/gpio.c M src/mainboard/google/zork/variants/trembyle/gpio.c M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/intel/glkrvp/romstage.c M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/strago/gpio.c M src/mainboard/intel/strago/ramstage.c M src/mainboard/intel/strago/romstage.c M src/soc/mediatek/mt8173/emi.c M src/soc/qualcomm/common/qclib.c 34 files changed, 0 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 384e44b..ceba219 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <boardid.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index b9f2830..5ea0485 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index ab7bc8c..7d29df8 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -4,7 +4,6 @@ #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> -#include <boardid.h> void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) { diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index cd55c93..39a3428 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <boot/coreboot_tables.h> #include <device/device.h> #include <gpio.h> diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c index 5b80203..f2a3a78 100644 --- a/src/mainboard/google/hatch/variants/palkia/memory.c +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -2,7 +2,6 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> -#include <boardid.h> #include <gpio.h> #include <soc/cnl_memcfg_init.h> #include <string.h> diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index ec9ae3a..349fe34 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -2,7 +2,6 @@ #include <chip.h> #include <amdblocks/agesawrapper.h> -#include <boardid.h> #include <gpio.h> #include <console/console.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 4b50d49..79fd478 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -2,7 +2,6 @@ #include <amdblocks/agesawrapper.h> #include <variant/gpio.h> -#include <boardid.h> #include <chip.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 8628074..22d8bb8 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/southbridge.h> -#include <boardid.h> #include <variant/gpio.h> /* diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index d01c513..599907e 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index d01c513..599907e 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index 9c8e2a6..ea488ad 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 1a8a371..635d721 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <boardid.h> #include <sar.h> #include <baseboard/variants.h> #include <delay.h> diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 8148dce..6dbc74a 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c index e813fb1..089b28a 100644 --- a/src/mainboard/google/octopus/variants/lick/gpio.c +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 6644022..26a7e90 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index 0b658a4..948ce8f 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio early_gpio_table[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 12d2890..473ffb1 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/smi.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a2ad517..341357e 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -8,7 +8,6 @@ #include <soc/gpio.h> #include <soc/smi.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index ae2d02a..2452a1d 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index 2b46938..a71aa78 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 7f9582c..aeebd07 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index f86d926..295fb21 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/gumboz/gpio.c b/src/mainboard/google/zork/variants/gumboz/gpio.c index aac25bb..501c144 100644 --- a/src/mainboard/google/zork/variants/gumboz/gpio.c +++ b/src/mainboard/google/zork/variants/gumboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 9b36e37..778c6e4 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/shuboz/gpio.c b/src/mainboard/google/zork/variants/shuboz/gpio.c index 0fd867e..db20e44 100644 --- a/src/mainboard/google/zork/variants/shuboz/gpio.c +++ b/src/mainboard/google/zork/variants/shuboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index 4d73ea0..0546df4 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index c6ef161..5c918fd 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index f1e544c..868a4c6 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> #include <baseboard/variants.h> -#include <boardid.h> #include <soc/meminit.h> #include <soc/romstage.h> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index a600d0a..9f8187f 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -8,7 +8,6 @@ #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/device_nvs.h> -#include <boardid.h> #include "onboard.h" void mainboard_fill_gnvs(struct global_nvs *gnvs) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index d3d6168..0e7f88c 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -2,7 +2,6 @@ #include "irqroute.h" #include <soc/gpio.h> -#include <boardid.h> #include "onboard.h" #include "gpio.h" diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index eac843d..e7ed500 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/ramstage.h> -#include <boardid.h> #include "onboard.h" void mainboard_silicon_init_params(SILICON_INIT_UPD *params) diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 0bb4476..331db04 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -2,7 +2,6 @@ #include <soc/romstage.h> #include "onboard.h" -#include <boardid.h> void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index aa8079e..b3a9693 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <boardid.h> #include <console/console.h> #include <soc/addressmap.h> #include <soc/dramc_common.h> diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 9358890..daea209 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -2,7 +2,6 @@ #include <console/cbmem_console.h> #include <cbmem.h> -#include <boardid.h> #include <bootmode.h> #include <string.h> #include <fmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Gerrit-Change-Number: 50183 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021