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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49382 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037 ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037 List of changes: 1. FSP-M Header: - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 219 insertions(+), 215 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 0e9ca02..d042172 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -595,262 +595,262 @@ /** Offset 0x038F - Reserved **/ - UINT8 Reserved21[11]; + UINT8 Reserved21[3]; -/** Offset 0x039A - BiosGuard +/** Offset 0x0392 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS **/ UINT8 BiosGuard; -/** Offset 0x039B +/** Offset 0x0393 **/ UINT8 BiosGuardToolsInterface; -/** Offset 0x039C - Reserved +/** Offset 0x0394 - Reserved **/ UINT8 Reserved22[4]; -/** Offset 0x03A0 - PrmrrSize +/** Offset 0x0398 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable **/ UINT32 PrmrrSize; -/** Offset 0x03A4 - SinitMemorySize +/** Offset 0x039C - SinitMemorySize Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable **/ UINT32 SinitMemorySize; -/** Offset 0x03A8 - Reserved +/** Offset 0x03A0 - Reserved **/ UINT8 Reserved23[8]; -/** Offset 0x03B0 - TxtHeapMemorySize +/** Offset 0x03A8 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable **/ UINT32 TxtHeapMemorySize; -/** Offset 0x03B4 - TxtDprMemorySize +/** Offset 0x03AC - TxtDprMemorySize Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable **/ UINT32 TxtDprMemorySize; -/** Offset 0x03B8 - Reserved +/** Offset 0x03B0 - Reserved **/ - UINT8 Reserved24[614]; + UINT8 Reserved24[625]; -/** Offset 0x061E - Number of RsvdSmbusAddressTable. +/** Offset 0x0621 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x061F - Reserved +/** Offset 0x0622 - Reserved **/ - UINT8 Reserved25[4]; + UINT8 Reserved25[3]; -/** Offset 0x0623 - Usage type for ClkSrc +/** Offset 0x0625 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ UINT8 PcieClkSrcUsage[18]; -/** Offset 0x0635 - Reserved +/** Offset 0x0637 - Reserved **/ UINT8 Reserved26[14]; -/** Offset 0x0643 - ClkReq-to-ClkSrc mapping +/** Offset 0x0645 - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[18]; -/** Offset 0x0655 - Reserved +/** Offset 0x0657 - Reserved **/ - UINT8 Reserved27[91]; + UINT8 Reserved27[93]; -/** Offset 0x06B0 - Enable PCIE RP Mask +/** Offset 0x06B4 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpEnableMask; -/** Offset 0x06B4 - Reserved +/** Offset 0x06B8 - Reserved **/ UINT8 Reserved28[2]; -/** Offset 0x06B6 - Enable HD Audio Link +/** Offset 0x06BA - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x06B7 - Reserved +/** Offset 0x06BB - Reserved **/ UINT8 Reserved29[3]; -/** Offset 0x06BA - Enable HD Audio DMIC_N Link +/** Offset 0x06BE - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x06BC - DMIC<N> ClkA Pin Muxing (N - DMIC number) +/** Offset 0x06C0 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* **/ UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; -/** Offset 0x06C4 - DMIC<N> ClkB Pin Muxing +/** Offset 0x06C8 - DMIC<N> ClkB Pin Muxing Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* **/ UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; -/** Offset 0x06CC - Enable HD Audio DSP +/** Offset 0x06D0 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x06CD - Reserved +/** Offset 0x06D1 - Reserved **/ UINT8 Reserved30[3]; -/** Offset 0x06D0 - DMIC<N> Data Pin Muxing +/** Offset 0x06D4 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* **/ UINT32 PchHdaAudioLinkDmicDataPinMux[2]; -/** Offset 0x06D8 - Enable HD Audio SSP0 Link +/** Offset 0x06DC - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[6]; -/** Offset 0x06DE - Enable HD Audio SoundWire#N Link +/** Offset 0x06E2 - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[4]; -/** Offset 0x06E2 - iDisp-Link Frequency +/** Offset 0x06E6 - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x06E3 - iDisp-Link T-mode +/** Offset 0x06E7 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x06E4 - iDisplay Audio Codec disconnection +/** Offset 0x06E8 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x06E5 - Debug Interfaces +/** Offset 0x06E9 - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x06E6 - Serial Io Uart Debug Controller Number +/** Offset 0x06EA - Serial Io Uart Debug Controller Number Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x06E7 - Reserved +/** Offset 0x06EB - Reserved **/ UINT8 Reserved31[13]; -/** Offset 0x06F4 - ISA Serial Base selection +/** Offset 0x06F8 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x06F5 - Reserved +/** Offset 0x06F9 - Reserved **/ UINT8 Reserved32[4]; -/** Offset 0x06F9 - MRC Safe Config +/** Offset 0x06FD - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS **/ UINT8 MrcSafeConfig; -/** Offset 0x06FA - TCSS Thunderbolt PCIE Root Port 0 Enable +/** Offset 0x06FE - TCSS Thunderbolt PCIE Root Port 0 Enable Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie0En; -/** Offset 0x06FB - TCSS Thunderbolt PCIE Root Port 1 Enable +/** Offset 0x06FF - TCSS Thunderbolt PCIE Root Port 1 Enable Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie1En; -/** Offset 0x06FC - TCSS Thunderbolt PCIE Root Port 2 Enable +/** Offset 0x0700 - TCSS Thunderbolt PCIE Root Port 2 Enable Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie2En; -/** Offset 0x06FD - TCSS Thunderbolt PCIE Root Port 3 Enable +/** Offset 0x0701 - TCSS Thunderbolt PCIE Root Port 3 Enable Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie3En; -/** Offset 0x06FE - TCSS USB HOST (xHCI) Enable +/** Offset 0x0702 - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below $EN_DIS **/ UINT8 TcssXhciEn; -/** Offset 0x06FF - TCSS USB DEVICE (xDCI) Enable +/** Offset 0x0703 - TCSS USB DEVICE (xDCI) Enable Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled $EN_DIS **/ UINT8 TcssXdciEn; -/** Offset 0x0700 - TCSS DMA0 Enable +/** Offset 0x0704 - TCSS DMA0 Enable Set TCSS DMA0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma0En; -/** Offset 0x0701 - TCSS DMA1 Enable +/** Offset 0x0705 - TCSS DMA1 Enable Set TCSS DMA1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma1En; -/** Offset 0x0702 - Reserved +/** Offset 0x0706 - Reserved **/ UINT8 Reserved33[2]; -/** Offset 0x0704 - Early Command Training +/** Offset 0x0708 - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x0705 - Reserved +/** Offset 0x0709 - Reserved **/ UINT8 Reserved34[65]; -/** Offset 0x0746 - Ch Hash Mask +/** Offset 0x074A - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC **/ UINT16 ChHashMask; -/** Offset 0x0748 - Reserved +/** Offset 0x074C - Reserved **/ - UINT8 Reserved35[64]; + UINT8 Reserved35[66]; -/** Offset 0x0788 - PcdSerialDebugLevel +/** Offset 0x078E - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -859,91 +859,91 @@ **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0789 - Reserved +/** Offset 0x078F - Reserved **/ UINT8 Reserved36[2]; -/** Offset 0x078B - Safe Mode Support +/** Offset 0x0791 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) $EN_DIS **/ UINT8 SafeMode; -/** Offset 0x078C - Reserved +/** Offset 0x0792 - Reserved **/ UINT8 Reserved37[2]; -/** Offset 0x078E - TCSS USB Port Enable +/** Offset 0x0794 - TCSS USB Port Enable Bitmap for per port enabling **/ UINT8 UsbTcPortEnPreMem; -/** Offset 0x078F - Reserved +/** Offset 0x0795 - Reserved **/ - UINT8 Reserved38[35]; + UINT8 Reserved38[33]; -/** Offset 0x07B2 - Command Pins Mapping +/** Offset 0x07B6 - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. **/ UINT8 Lp5CccConfig; -/** Offset 0x07B3 - Reserved +/** Offset 0x07B7 - Reserved **/ - UINT8 Reserved39[14]; + UINT8 Reserved39[12]; -/** Offset 0x07C1 - Skip external display device scanning +/** Offset 0x07C3 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x07C2 - Reserved +/** Offset 0x07C4 - Reserved **/ UINT8 Reserved40; -/** Offset 0x07C3 - Lock PCU Thermal Management registers +/** Offset 0x07C5 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x07C4 - Reserved +/** Offset 0x07C6 - Reserved **/ - UINT8 Reserved41[129]; + UINT8 Reserved41[131]; -/** Offset 0x0845 - Skip CPU replacement check +/** Offset 0x0849 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x0846 - Reserved +/** Offset 0x084A - Reserved **/ UINT8 Reserved42[292]; -/** Offset 0x096A - Serial Io Uart Debug Mode +/** Offset 0x096E - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x096B - Reserved +/** Offset 0x096F - Reserved **/ - UINT8 Reserved43[183]; + UINT8 Reserved43[185]; -/** Offset 0x0A22 - GPIO Override +/** Offset 0x0A28 - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use **/ UINT8 GpioOverride; -/** Offset 0x0A23 - Reserved +/** Offset 0x0A29 - Reserved **/ - UINT8 Reserved44[349]; + UINT8 Reserved44[23]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -962,11 +962,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0B80 +/** Offset 0x0A40 **/ - UINT8 UnusedUpdSpace29[6]; + UINT8 UnusedUpdSpace25[6]; -/** Offset 0x0B86 +/** Offset 0x0A46 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index d9cbc5b..8a92e00 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -377,40 +377,44 @@ **/ UINT8 CnviMode; -/** Offset 0x043D - CNVi BT Core +/** Offset 0x043D - Reserved +**/ + UINT8 Reserved15; + +/** Offset 0x043E - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x043E - CNVi BT Audio Offload +/** Offset 0x043F - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x043F - Reserved +/** Offset 0x0440 - Reserved **/ - UINT8 Reserved15; + UINT8 Reserved16[4]; -/** Offset 0x0440 - CNVi RF_RESET pin muxing +/** Offset 0x0444 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. **/ UINT32 CnviRfResetPinMux; -/** Offset 0x0444 - CNVi CLKREQ pin muxing +/** Offset 0x0448 - CNVi CLKREQ pin muxing Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default) or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in GpioPins*.h. **/ UINT32 CnviClkreqPinMux; -/** Offset 0x0448 - Reserved +/** Offset 0x044C - Reserved **/ - UINT8 Reserved16[172]; + UINT8 Reserved17[172]; -/** Offset 0x04F4 - CdClock Frequency selection +/** Offset 0x04F8 - CdClock Frequency selection 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, @@ -418,293 +422,293 @@ **/ UINT8 CdClock; -/** Offset 0x04F5 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x04F9 - Enable/Disable PeiGraphicsPeimInit Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x04F6 - Enable D3 Hot in TCSS +/** Offset 0x04FA - Enable D3 Hot in TCSS This policy will enable/disable D3 hot support in IOM $EN_DIS **/ UINT8 D3HotEnable; -/** Offset 0x04F7 - Reserved +/** Offset 0x04FB - Reserved **/ - UINT8 Reserved17; + UINT8 Reserved18; -/** Offset 0x04F8 - TypeC port GPIO setting +/** Offset 0x04FC - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl = AlderLake) **/ UINT32 IomTypeCPortPadCfg[8]; -/** Offset 0x0518 - Reserved +/** Offset 0x051C - Reserved **/ - UINT8 Reserved18[8]; + UINT8 Reserved19[8]; -/** Offset 0x0520 - Enable D3 Cold in TCSS +/** Offset 0x0524 - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM $EN_DIS **/ UINT8 D3ColdEnable; -/** Offset 0x0521 - Reserved +/** Offset 0x0525 - Reserved **/ - UINT8 Reserved19[8]; + UINT8 Reserved20[16]; -/** Offset 0x0529 - Enable VMD controller - Enable/disable to VMD controller.0: Disable(Default); 1: Enable +/** Offset 0x0535 - Enable VMD controller + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) $EN_DIS **/ UINT8 VmdEnable; -/** Offset 0x052A - Reserved +/** Offset 0x0536 - Reserved **/ - UINT8 Reserved20[120]; + UINT8 Reserved21[120]; -/** Offset 0x05A2 - TCSS Aux Orientation Override Enable +/** Offset 0x05AE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x05A4 - TCSS HSL Orientation Override Enable +/** Offset 0x05B0 - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x05A6 - Reserved +/** Offset 0x05B2 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved22; -/** Offset 0x05A7 - ITBT Root Port Enable +/** Offset 0x05B3 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable 0:Disable, 1:Enable **/ UINT8 ITbtPcieRootPortEn[4]; -/** Offset 0x05AB - Reserved +/** Offset 0x05B7 - Reserved **/ - UINT8 Reserved22[3]; + UINT8 Reserved23[3]; -/** Offset 0x05AE - ITbtConnectTopology Timeout value +/** Offset 0x05BA - ITbtConnectTopology Timeout value ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms. **/ UINT16 ITbtConnectTopologyTimeoutInMs; -/** Offset 0x05B0 - Reserved +/** Offset 0x05BC - Reserved **/ - UINT8 Reserved23[7]; + UINT8 Reserved24[7]; -/** Offset 0x05B7 - Enable/Disable PTM +/** Offset 0x05C3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports $EN_DIS **/ UINT8 PtmEnabled[4]; -/** Offset 0x05BB - Reserved +/** Offset 0x05C7 - Reserved **/ - UINT8 Reserved24[200]; + UINT8 Reserved25[200]; -/** Offset 0x0683 - Skip Multi-Processor Initialization +/** Offset 0x068F - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x0684 - Reserved +/** Offset 0x0690 - Reserved **/ - UINT8 Reserved25[8]; + UINT8 Reserved26[8]; -/** Offset 0x068C - CpuMpPpi +/** Offset 0x0698 - CpuMpPpi Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; -/** Offset 0x0690 - Reserved +/** Offset 0x069C - Reserved **/ - UINT8 Reserved26[74]; + UINT8 Reserved27[70]; -/** Offset 0x06DA - Enable Power Optimizer +/** Offset 0x06E2 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x06DB - Reserved +/** Offset 0x06E3 - Reserved **/ - UINT8 Reserved27[33]; + UINT8 Reserved28[33]; -/** Offset 0x06FC - Enable PCH ISH SPI Cs0 pins assigned +/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiCs0Enable[1]; -/** Offset 0x06FD - Reserved +/** Offset 0x0705 - Reserved **/ - UINT8 Reserved28[2]; + UINT8 Reserved29[2]; -/** Offset 0x06FF - Enable PCH ISH SPI pins assigned +/** Offset 0x0707 - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiEnable[1]; -/** Offset 0x0700 - Enable PCH ISH UART pins assigned +/** Offset 0x0708 - Enable PCH ISH UART pins assigned Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshUartEnable[2]; -/** Offset 0x0702 - Enable PCH ISH I2C pins assigned +/** Offset 0x070A - Enable PCH ISH I2C pins assigned Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI2cEnable[3]; -/** Offset 0x0705 - Enable PCH ISH GP pins assigned +/** Offset 0x070D - Enable PCH ISH GP pins assigned Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshGpEnable[8]; -/** Offset 0x070D - Reserved +/** Offset 0x0715 - Reserved **/ - UINT8 Reserved29[2]; + UINT8 Reserved30[2]; -/** Offset 0x070F - Enable LOCKDOWN BIOS LOCK +/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x0710 - Reserved +/** Offset 0x0718 - Reserved **/ - UINT8 Reserved30[2]; + UINT8 Reserved31[2]; -/** Offset 0x0712 - RTC Cmos Memory Lock +/** Offset 0x071A - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x0713 - Enable PCIE RP HotPlug +/** Offset 0x071B - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[28]; -/** Offset 0x072F - Reserved +/** Offset 0x0737 - Reserved **/ - UINT8 Reserved31[56]; + UINT8 Reserved32[56]; -/** Offset 0x0767 - Enable PCIE RP Clk Req Detect +/** Offset 0x076F - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[28]; -/** Offset 0x0783 - PCIE RP Advanced Error Report +/** Offset 0x078B - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[28]; -/** Offset 0x079F - Reserved +/** Offset 0x07A7 - Reserved **/ - UINT8 Reserved32[196]; + UINT8 Reserved33[196]; -/** Offset 0x0863 - PCIE RP Max Payload +/** Offset 0x086B - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[28]; -/** Offset 0x087F - Touch Host Controller Port 0 Assignment +/** Offset 0x0887 - Touch Host Controller Port 0 Assignment Assign THC Port 0 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 **/ UINT8 ThcPort0Assignment; -/** Offset 0x0880 - Reserved +/** Offset 0x0888 - Reserved **/ - UINT8 Reserved33[5]; + UINT8 Reserved34[5]; -/** Offset 0x0885 - Touch Host Controller Port 1 Assignment +/** Offset 0x088D - Touch Host Controller Port 1 Assignment Assign THC Port 1 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcPort1Assignment; -/** Offset 0x0886 - Reserved +/** Offset 0x088E - Reserved **/ - UINT8 Reserved34[91]; + UINT8 Reserved35[91]; -/** Offset 0x08E1 - PCIE RP Aspm +/** Offset 0x08E9 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[28]; -/** Offset 0x08FD - PCIE RP L1 Substates +/** Offset 0x0905 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[28]; -/** Offset 0x0919 - Reserved +/** Offset 0x0921 - Reserved **/ - UINT8 Reserved35[28]; + UINT8 Reserved36[28]; -/** Offset 0x0935 - PCIE RP Ltr Enable +/** Offset 0x093D - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[28]; -/** Offset 0x0951 - Reserved +/** Offset 0x0959 - Reserved **/ - UINT8 Reserved36[132]; + UINT8 Reserved37[132]; -/** Offset 0x09D5 - PCH Sata Pwr Opt Enable +/** Offset 0x09DD - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x09D6 - Reserved +/** Offset 0x09DE - Reserved **/ - UINT8 Reserved37[50]; + UINT8 Reserved38[50]; -/** Offset 0x0A08 - Enable SATA Port DmVal +/** Offset 0x0A10 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x0A10 - Enable SATA Port DmVal +/** Offset 0x0A18 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x0A20 - Reserved +/** Offset 0x0A28 - Reserved **/ - UINT8 Reserved38[62]; + UINT8 Reserved39[62]; -/** Offset 0x0A5E - USB2 Port Over Current Pin +/** Offset 0x0A66 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0A6E - USB3 Port Over Current Pin +/** Offset 0x0A76 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0A78 - Reserved +/** Offset 0x0A80 - Reserved **/ - UINT8 Reserved39[16]; + UINT8 Reserved40[16]; -/** Offset 0x0A88 - Enable 8254 Static Clock Gating +/** Offset 0x0A90 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -712,7 +716,7 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x0A89 - Enable 8254 Static Clock Gating On S3 +/** Offset 0x0A91 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -720,22 +724,22 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0A8A - Reserved +/** Offset 0x0A92 - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved41; -/** Offset 0x0A8B - Hybrid Storage Detection and Configuration Mode +/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled 0: Disabled, 1: Dynamic Configuration **/ UINT8 HybridStorageMode; -/** Offset 0x0A8C - Reserved +/** Offset 0x0A94 - Reserved **/ - UINT8 Reserved41[93]; + UINT8 Reserved42[93]; -/** Offset 0x0AE9 - Enable PS_ON. +/** Offset 0x0AF1 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -743,29 +747,29 @@ **/ UINT8 PsOnEnable; -/** Offset 0x0AEA - Reserved +/** Offset 0x0AF2 - Reserved **/ - UINT8 Reserved42[318]; + UINT8 Reserved43[318]; -/** Offset 0x0C28 - RpPtmBytes +/** Offset 0x0C30 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0C2C - Reserved +/** Offset 0x0C34 - Reserved **/ - UINT8 Reserved43[95]; + UINT8 Reserved44[95]; -/** Offset 0x0C8B - Enable/Disable IGFX PmSupport +/** Offset 0x0C93 - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0C8C - Reserved +/** Offset 0x0C94 - Reserved **/ - UINT8 Reserved44; + UINT8 Reserved45; -/** Offset 0x0C8D - GT Frequency Limit +/** Offset 0x0C95 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -779,22 +783,22 @@ **/ UINT8 GtFreqMax; -/** Offset 0x0C8E - Reserved +/** Offset 0x0C96 - Reserved **/ - UINT8 Reserved45[24]; + UINT8 Reserved46[24]; -/** Offset 0x0CA6 - Enable or Disable HWP +/** Offset 0x0CAE - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0CA7 - Reserved +/** Offset 0x0CAF - Reserved **/ - UINT8 Reserved46[8]; + UINT8 Reserved47[8]; -/** Offset 0x0CAF - TCC Activation Offset +/** Offset 0x0CB7 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -802,63 +806,63 @@ **/ UINT8 TccActivationOffset; -/** Offset 0x0CB0 - Reserved +/** Offset 0x0CB8 - Reserved **/ - UINT8 Reserved47[34]; + UINT8 Reserved48[34]; -/** Offset 0x0CD2 - Enable or Disable CPU power states (C-states) +/** Offset 0x0CDA - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0CD3 - Reserved +/** Offset 0x0CDB - Reserved **/ - UINT8 Reserved48[196]; + UINT8 Reserved49[196]; -/** Offset 0x0D97 - Enable LOCKDOWN SMI +/** Offset 0x0D9F - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0D98 - Enable LOCKDOWN BIOS Interface +/** Offset 0x0DA0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0D99 - Unlock all GPIO pads +/** Offset 0x0DA1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0D9A - Reserved +/** Offset 0x0DA2 - Reserved **/ - UINT8 Reserved49[2]; + UINT8 Reserved50[2]; -/** Offset 0x0D9C - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0DD4 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DDC - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0E0C - Reserved +/** Offset 0x0E14 - Reserved **/ - UINT8 Reserved50[313]; + UINT8 Reserved51[313]; -/** Offset 0x0F45 - LpmStateEnableMask +/** Offset 0x0F4D - LpmStateEnableMask **/ UINT8 LpmStateEnableMask; -/** Offset 0x0F46 - Reserved +/** Offset 0x0F4E - Reserved **/ - UINT8 Reserved51[698]; + UINT8 Reserved52[122]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -877,11 +881,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x1200 +/** Offset 0x0FC8 **/ - UINT8 UnusedUpdSpace45[6]; + UINT8 UnusedUpdSpace43[6]; -/** Offset 0x1206 +/** Offset 0x0FCE **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/49382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33 Gerrit-Change-Number: 49382 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Update gpio config and device tree fo...
by Tao Xia (Code Review) 03 Feb '21

03 Feb '21

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50262 ) Change subject: mb/google/dedede/var/sasukette: Update gpio config and device tree for sasukette ...................................................................... mb/google/dedede/var/sasukette: Update gpio config and device tree for sasukette Update sasukette gpio config and device tree override to match schematics. BUG=b:177385043, b:177479444, b:177348842, b:177351873 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I9b73c660a304fa64d7cc9bf2df050d4e5a5c36fc Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> --- A src/mainboard/google/dedede/variants/sasukette/Makefile.inc A src/mainboard/google/dedede/variants/sasukette/gpio.c M src/mainboard/google/dedede/variants/sasukette/overridetree.cb A src/mainboard/google/dedede/variants/sasukette/variant.c 4 files changed, 137 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/50262/1 diff --git a/src/mainboard/google/dedede/variants/sasukette/Makefile.inc b/src/mainboard/google/dedede/variants/sasukette/Makefile.inc new file mode 100644 index 0000000..fd60a18 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasukette/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/sasukette/gpio.c b/src/mainboard/google/dedede/variants/sasukette/gpio.c new file mode 100644 index 0000000..dc8c169 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasukette/gpio.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN */ + PAD_CFG_GPO(GPP_A10, 0, PLTRST), + + /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_B7, NONE, DEEP, LEVEL, INVERT), + + /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D15 : EN_PP3300_CAMERA */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + + /* H17 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 404024b..2b310ce 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -36,7 +36,88 @@ }, }" + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + device domain 0 on - device pci 15.0 on end + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D15)" + register "enable_delay_ms" = "20" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0A00"" + register "generic.desc" = ""SYNA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7288"" + register "generic.desc" = ""GXTP Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SPPT2600"" + register "generic.desc" = ""SPPT Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end #I2C 0 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end #I2C 4 + device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/google/dedede/variants/sasukette/variant.c b/src/mainboard/google/dedede/variants/sasukette/variant.c new file mode 100644 index 0000000..22caa06 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasukette/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <delay.h> +#include <gpio.h> + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(20); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b73c660a304fa64d7cc9bf2df050d4e5a5c36fc Gerrit-Change-Number: 50262 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: add UPD for USB3 phy setting adjust
by chris wang (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Chris Wang, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50240 to look at the new patch set (#6). Change subject: soc/amd/picasso: add UPD for USB3 phy setting adjust ...................................................................... soc/amd/picasso: add UPD for USB3 phy setting adjust add UPD for USB3 phy setting adjust Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL -Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN -Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build/verify the valule will been apply on dirinboz Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c M src/vendorcode/amd/fsp/picasso/FspsUpd.h 3 files changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/50240/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 6 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/cezanne: Replace the PSP Bootloader with AB version
by Felix Held (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50251 ) Change subject: soc/amd/cezanne: Replace the PSP Bootloader with AB version ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: > This need to wait for PSP updating. TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is laready present in 3rdparty/amd_blobs/cezanne/PSP/. i can test later if this works with the current binaries -- To view, visit https://review.coreboot.org/c/coreboot/+/50251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcee65e7dcc30d7ee7a58338f439eaee5cd942e Gerrit-Change-Number: 50251 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 03 Feb 2021 14:22:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)
by Felix Held (Code Review) 03 Feb '21

03 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50227 ) Change subject: amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) ...................................................................... amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/fw.cfg M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 4 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 189bc9d..277707d 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -29,6 +29,7 @@ KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 8b54876..3d33d70 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -261,6 +261,7 @@ { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 }, { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 }, { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 }, { .type = AMD_ABL0, .level = PSP_BOTH }, { .type = AMD_ABL1, .level = PSP_BOTH }, { .type = AMD_ABL2, .level = PSP_BOTH }, diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index b12b989..c8e7ef4 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -47,6 +47,7 @@ AMD_RPMC_NVRAM = 0x54, AMD_FW_DMCU_ERAM = 0x58, AMD_FW_DMCU_ISR = 0x59, + AMD_FW_PSP_BOOTLOADER_AB = 0x73, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, AMD_FW_XHCI, diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index b6e14a8..80d8d01 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -244,6 +244,9 @@ } else if (strcmp(fw_name, "RPMC_FILE") == 0) { fw_type = AMD_RPMC_NVRAM; subprog = 0; + } else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { + fw_type = AMD_FW_PSP_BOOTLOADER_AB; + subprog = 0; } else { fw_type = AMD_FW_INVALID; /* TODO: Add more */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Gerrit-Change-Number: 50227 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/fch: add missing iomap.h include
by Felix Held (Code Review) 03 Feb '21

03 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50260 ) Change subject: soc/amd/picasso/fch: add missing iomap.h include ...................................................................... soc/amd/picasso/fch: add missing iomap.h include Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iea9666fe4f61fb503fee4060a90ec75e2d70c24f --- M src/soc/amd/picasso/fch.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/50260/1 diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index fa99db8..8cc0c13 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -17,6 +17,7 @@ #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea9666fe4f61fb503fee4060a90ec75e2d70c24f Gerrit-Change-Number: 50260 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST]: ADL PO changes for memory
by Maulik V Vaghela (Code Review) 03 Feb '21

03 Feb '21

Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50139 ) Change subject: [TEST]: ADL PO changes for memory ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36368cf62f4ac4478b82156bb75681ed9c53255d Gerrit-Change-Number: 50139 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Dana Alkattan <dana.alkattan(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: [TEST]:soc/intel/alderlake: Increase VBT size to 9Kb for ADL.
by Maulik V Vaghela (Code Review) 03 Feb '21

03 Feb '21

Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50197 ) Change subject: [TEST]:soc/intel/alderlake: Increase VBT size to 9Kb for ADL. ...................................................................... Abandoned Included as part of PO changes patch -- To view, visit https://review.coreboot.org/c/coreboot/+/50197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I887a5f923854f736bc7d74d60e18aa6e23b2063e Gerrit-Change-Number: 50197 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Dana Alkattan <dana.alkattan(a)intel.com> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: [TEST] Changes to enable display on ADL_M
by Maulik V Vaghela (Code Review) 03 Feb '21

03 Feb '21

Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50233 ) Change subject: [TEST] Changes to enable display on ADL_M ...................................................................... Abandoned Included as part of base patch -- To view, visit https://review.coreboot.org/c/coreboot/+/50233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia19753e0183f637808a93ae02f784042f15fa30e Gerrit-Change-Number: 50233 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: [TEST]: Changes to enable NVME on ADL-M
by Maulik V Vaghela (Code Review) 03 Feb '21

03 Feb '21

Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50234 ) Change subject: [TEST]: Changes to enable NVME on ADL-M ...................................................................... Abandoned Included as part of base patch -- To view, visit https://review.coreboot.org/c/coreboot/+/50234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9649f4b7e01c97957e98be76ae07865087dbc884 Gerrit-Change-Number: 50234 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: abandon

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coreboot-gerrit February 2021