coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/picasso: clean up and re-sort UPD table
by Martin Roth (Code Review) 03 Feb '21

03 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50212 ) Change subject: soc/amd/picasso: clean up and re-sort UPD table ...................................................................... soc/amd/picasso: clean up and re-sort UPD table Clean up the unused UPD and re-sort the table, and also update the new phy parameter in the soc code and overridetree. remove: EDpPhySel EDpVersion rename: DpPhyOverride -> edp_phy_override EDpPhySel -> edp_physel DpVsPemphLevel -> edp_dp_vs_pemph_level MarginDeemPh -> edp_margin_deemph Deemph6db4 -> edp_deemph_6db_4 BoostAdj -> edp_boost_adj eDP phy setting: DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004b COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80 BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c M src/vendorcode/amd/fsp/picasso/FspsUpd.h 4 files changed, 37 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index c3afe13..ad5cc7e 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -24,7 +24,17 @@ register "telemetry_vddcr_soc_offset" = "168" # eDP phy tuning settings - register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + register "edp_phy_override" = "ENABLE_EDP_TUNINGSET" + + # bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 + register "edp_physel" = "0x1" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x00, + .margin_deemph = 0x004b, + .deemph_6db4 = 0x0, + .boostadj = 0x80, + }" # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, # and "0" as default value @@ -38,13 +48,6 @@ register "pwrdown_bloff_to_varybloff" = "5" register "min_allowed_bl_level" = "0" - register "edp_tuningset" = "{ - .dp_vs_pemph_level = 0x0, - .deemph_6db4 = 0x004b, - .boostadj = 0x0, - .margin_deemph = 0x80, - }" - # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 244d783..9a7d2a5 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -253,7 +253,9 @@ bool acp_i2s_use_external_48mhz_osc; /* eDP phy tuning settings */ - uint8_t dp_phy_override; + uint16_t edp_phy_override; + /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ + uint8_t edp_physel; struct { uint8_t dp_vs_pemph_level; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 731a564..df5e1e6 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -145,12 +145,13 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg, const struct soc_amd_picasso_config *cfg) { - if (cfg->dp_phy_override & ENABLE_EDP_TUNINGSET) { - scfg->DpPhyOverride = cfg->dp_phy_override; - scfg->DpVsPemphLevel = cfg->edp_tuningset.dp_vs_pemph_level; - scfg->MarginDeemPh = cfg->edp_tuningset.margin_deemph; - scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4; - scfg->BoostAdj = cfg->edp_tuningset.boostadj; + if (cfg->edp_phy_override & ENABLE_EDP_TUNINGSET) { + scfg->edp_phy_override = cfg->edp_phy_override; + scfg->edp_physel = cfg->edp_physel; + scfg->edp_dp_vs_pemph_level = cfg->edp_tuningset.dp_vs_pemph_level; + scfg->edp_margin_deemph = cfg->edp_tuningset.margin_deemph; + scfg->edp_deemph_6db_4 = cfg->edp_tuningset.deemph_6db4; + scfg->edp_boost_adj = cfg->edp_tuningset.boostadj; } if (cfg->edp_pwr_adjust_enable) { scfg->pwron_digon_to_de = cfg->pwron_digon_to_de; diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index ee516f8..aac6fdb 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -39,26 +39,22 @@ /** Offset 0x0124**/ uint32_t gnb_ioapic_base; /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4; - /** Offset 0x0131**/ uint8_t DpPhyOverride; - /** Offset 0x0132**/ uint16_t EDpPhySel; - /** Offset 0x0134**/ uint8_t EDpVersion; - /** Offset 0x0135**/ uint8_t EDpTableSize; - /** Offset 0x0136**/ uint8_t DpVsPemphLevel; - /** Offset 0x0137**/ uint16_t MarginDeemPh; - /** Offset 0x0139**/ uint8_t Deemph6db4; - /** Offset 0x013A**/ uint8_t BoostAdj; - /** Offset 0x013B**/ uint16_t backlight_pwmhz; - /** Offset 0x013D**/ uint8_t pwron_digon_to_de; - /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; - /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; - /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; - /** Offset 0x0141**/ uint8_t pwroff_delay; - /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; - /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; - /** Offset 0x0144**/ uint8_t min_allowed_bl_level; - /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; + /** Offset 0x012A**/ uint16_t edp_phy_override; + /** Offset 0x012C**/ uint8_t edp_physel; + /** Offset 0x012D**/ uint8_t edp_dp_vs_pemph_level; + /** Offset 0x012E**/ uint16_t edp_margin_deemph; + /** Offset 0x0130**/ uint8_t edp_deemph_6db_4; + /** Offset 0x0131**/ uint8_t edp_boost_adj; + /** Offset 0x0132**/ uint16_t backlight_pwmhz; + /** Offset 0x0134**/ uint8_t pwron_digon_to_de; + /** Offset 0x0135**/ uint8_t pwron_de_to_varybl; + /** Offset 0x0136**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0137**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0138**/ uint8_t pwroff_delay; + /** Offset 0x0139**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x013B**/ uint8_t min_allowed_bl_level; + /** Offset 0x013C**/ uint8_t UnusedUpdSpace0[20]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/50212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Gerrit-Change-Number: 50212 Gerrit-PatchSet: 7 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/variant/copano: support regular/numpad touchpad
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50129 ) Change subject: mb/google/volteer/variant/copano: support regular/numpad touchpad ...................................................................... mb/google/volteer/variant/copano: support regular/numpad touchpad Define the 25th bit of the fw_config for the regular touchpad and numpad touchpad selection. BUG=b:174027837 BRANCH=firmware-volteer-13672.B TEST=build pass Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Marco Chen <marcochen(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/copano/overridetree.cb 2 files changed, 18 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marco Chen: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index d74476a..ccde132 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -58,6 +58,10 @@ option BOOT_SATA_DISABLED 0 option BOOT_SATA_ENABLED 1 end + field TOUCHPAD 25 + option REGULAR_TOUCHPAD 0 + option NUMPAD_TOUCHPAD 1 + end end chip soc/intel/tigerlake diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index d4e0746..1192129 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -97,14 +97,26 @@ end end device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on + probe TOUCHPAD REGULAR_TOUCHPAD + end + end chip drivers/i2c/hid - register "generic.hid" = ""ELAN0000"" + register "generic.hid" = ""ELAN2701"" register "generic.desc" = ""ELAN Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" register "generic.wake" = "GPE0_DW2_15" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end + device i2c 15 on + probe TOUCHPAD NUMPAD_TOUCHPAD + end end end device ref pch_espi on -- To view, visit https://review.coreboot.org/c/coreboot/+/50129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663 Gerrit-Change-Number: 50129 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: clean up and re-sort UPD table
by Chris Wang (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Marshall Dawson, chris wang, EricR Lai, Felix Held. Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50212 ) Change subject: soc/amd/picasso: clean up and re-sort UPD table ...................................................................... Patch Set 6: (2 comments) Patchset: PS3: > @Eric […] Done File src/mainboard/google/zork/variants/vilboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50212/comment/0afaa9ed_b5ff3ee6 PS3, Line 34: .margin_deemph = 0x00CC, > ok Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/50212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Gerrit-Change-Number: 50212 Gerrit-PatchSet: 6 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Feb 2021 17:16:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Comment-In-Reply-To: chris wang <Chris.Wang(a)amd.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Create kracko variant
by Paul Fagerburg (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Martin Roth, Tony Huang, Wisley Chen, Karthik Ramasubramanian. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50255 ) Change subject: mb/google/dedede: Create kracko variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed Gerrit-Change-Number: 50255 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 17:12:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu-q35: Fix crash in CorebootPayloadPkg
by Angel Pons (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50267 ) Change subject: mb/emulation/qemu-q35: Fix crash in CorebootPayloadPkg ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50267/comment/f2720440_9572aa5c PS1, Line 7: Fix crash in CorebootPayloadPkg Mark TSEG region as reserved File src/mainboard/emulation/qemu-i440fx/northbridge.c: https://review.coreboot.org/c/coreboot/+/50267/comment/89039530_94c6634e PS1, Line 109: CONFIG(BOARD_EMULATION_QEMU_X86_Q35) There's the `q35` variable already https://review.coreboot.org/c/coreboot/+/50267/comment/87b07cf7_aedf8eae PS1, Line 111: size_t uintptr_t -- To view, visit https://review.coreboot.org/c/coreboot/+/50267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832 Gerrit-Change-Number: 50267 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 16:48:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu-q35: Fix crash in CorebootPayloadPkg
by Patrick Rudolph (Code Review) 03 Feb '21

03 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50267 ) Change subject: mb/emulation/qemu-q35: Fix crash in CorebootPayloadPkg ...................................................................... mb/emulation/qemu-q35: Fix crash in CorebootPayloadPkg Mark TSEG as reserved, which is done on other platforms as well. For some reason CorebootPayloadPkg crashes when using the region which is basically RAM. UefiPayloadPkg doesn't show this issue. Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/northbridge.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/50267/1 diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index f49d47da..9b47735 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -106,6 +106,14 @@ ram_resource(dev, idx++, 4 * 1024 * 1024, high); } + if (CONFIG(BOARD_EMULATION_QEMU_X86_Q35)) { + size_t tseg_size; + size_t tseg_base; + smm_region(&tseg_base, &tseg_size); + + reserved_ram_resource(dev, idx++, tseg_base / 1024, tseg_size / 1024); + } + /* Reserve I/O ports used by QEMU */ qemu_reserve_ports(dev, idx++, 0x0510, 0x02, "firmware-config"); qemu_reserve_ports(dev, idx++, 0x5658, 0x01, "vmware-port"); -- To view, visit https://review.coreboot.org/c/coreboot/+/50267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832 Gerrit-Change-Number: 50267 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/acpi/pm_state: add missing include
by Raul Rangel (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kyösti Mälkki, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50266 ) Change subject: soc/amd/common/block/acpi/pm_state: add missing include ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22862c2d29f130c741b4817dac00287ecfc71fa2 Gerrit-Change-Number: 50266 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Feb 2021 16:33:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/acpi/pm_state: add missing include
by Felix Held (Code Review) 03 Feb '21

03 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50266 ) Change subject: soc/amd/common/block/acpi/pm_state: add missing include ...................................................................... soc/amd/common/block/acpi/pm_state: add missing include Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I22862c2d29f130c741b4817dac00287ecfc71fa2 --- M src/soc/amd/common/block/acpi/pm_state.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/50266/1 diff --git a/src/soc/amd/common/block/acpi/pm_state.c b/src/soc/amd/common/block/acpi/pm_state.c index a009718..253f90f 100644 --- a/src/soc/amd/common/block/acpi/pm_state.c +++ b/src/soc/amd/common/block/acpi/pm_state.c @@ -2,6 +2,7 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpi_pm.h> +#include <amdblocks/acpi.h> #include <bootstate.h> #include <soc/acpi.h> #include <soc/nvs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22862c2d29f130c741b4817dac00287ecfc71fa2 Gerrit-Change-Number: 50266 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
by Tim Wawrzynczak (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50254 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Gerrit-Change-Number: 50254 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 16:26:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Configure Camera related GPIO as per schematics
by Varshit B Pandya (Code Review) 03 Feb '21

03 Feb '21

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50265 ) Change subject: mb/intel/adlrvp: Configure Camera related GPIO as per schematics ...................................................................... mb/intel/adlrvp: Configure Camera related GPIO as per schematics Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e --- M src/mainboard/intel/adlrvp/gpio_m.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/50265/1 diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 9246ac1..9d8ee3d 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -81,7 +81,20 @@ /* SNDW4_CLK */ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* SNDW4_DATA */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2) + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + /* IMGCLKOUT0 */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + /* IMGCLKOUT1 */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), }; void variant_configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/50265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e Gerrit-Change-Number: 50265 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021