coreboot-gerrit February 2021

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Change in coreboot[master]: sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER`
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50424 ) Change subject: sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER` ...................................................................... sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER` It is already set in `src/arch/x86/acpi.c` function `arch_fill_fadt`. Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/fadt.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/50424/1 diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index ee696ed..ba9e47d 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -58,7 +58,6 @@ ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_PCI_EXPRESS_WAKE | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_S4_RTC_VALID | -- To view, visit https://review.coreboot.org/c/coreboot/+/50424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69 Gerrit-Change-Number: 50424 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50423 ) Change subject: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros ...................................................................... sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros Tested with BUILD_TIMELESS=1, Lenovo G505s remains identical. Change-Id: I759bdef44f7ca0f35350901998f6820820005b38 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/sm.c 1 file changed, 0 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/50423/1 diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index a6b1464..6f9e03c 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -14,41 +14,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) - -#define BIT8 (1 << 8) -#define BIT9 (1 << 9) -#define BIT10 (1 << 10) -#define BIT11 (1 << 11) -#define BIT12 (1 << 12) -#define BIT13 (1 << 13) -#define BIT14 (1 << 14) -#define BIT15 (1 << 15) - -#define BIT16 (1 << 16) -#define BIT17 (1 << 17) -#define BIT18 (1 << 18) -#define BIT19 (1 << 19) -#define BIT20 (1 << 20) -#define BIT21 (1 << 21) -#define BIT22 (1 << 22) -#define BIT23 (1 << 23) -#define BIT24 (1 << 24) -#define BIT25 (1 << 25) -#define BIT26 (1 << 26) -#define BIT27 (1 << 27) -#define BIT28 (1 << 28) -#define BIT29 (1 << 29) -#define BIT30 (1 << 30) -#define BIT31 (1 << 31) - /* * HUDSON enables all USB controllers by default in SMBUS Control. * HUDSON enables SATA by default in SMBUS Control. -- To view, visit https://review.coreboot.org/c/coreboot/+/50423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759bdef44f7ca0f35350901998f6820820005b38 Gerrit-Change-Number: 50423 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/pi/hudson/pci.c: Remove empty init operation
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50422 ) Change subject: sb/amd/pi/hudson/pci.c: Remove empty init operation ...................................................................... sb/amd/pi/hudson/pci.c: Remove empty init operation Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/amd/pi/hudson/pci.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/50422/1 diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index 3dd0368..5e828f7 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -7,10 +7,6 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> -static void pci_init(struct device *dev) -{ -} - /* * Update the PCI devices with a valid IRQ number * that is set in the mainboard PCI_IRQ structures. @@ -38,7 +34,6 @@ .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, -- To view, visit https://review.coreboot.org/c/coreboot/+/50422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51 Gerrit-Change-Number: 50422 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/pi/hudson/imc.c: Remove duplicated comment
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50421 ) Change subject: sb/amd/pi/hudson/imc.c: Remove duplicated comment ...................................................................... sb/amd/pi/hudson/imc.c: Remove duplicated comment Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/amd/pi/hudson/imc.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/50421/1 diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index fd9a372..81b0e26 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -19,8 +19,6 @@ u8 reg8; /* Init Power Management Block 2 (PM2) Registers. * Check BKDG for AMD Family 16h for details. */ - /* Init Power Management Block 2 (PM2) Registers. - * Check BKDG for AMD Family 16h for details. */ pm2_write8(0, 0x06); pm2_write8(1, 0x06); pm2_write8(2, 0xf7); -- To view, visit https://review.coreboot.org/c/coreboot/+/50421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce Gerrit-Change-Number: 50421 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50415 ) Change subject: soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779 Gerrit-Change-Number: 50415 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Feb 2021 10:40:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable early LPC support in bootblock stage
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49929 ) Change subject: soc/amd/cezanne: Enable early LPC support in bootblock stage ...................................................................... Patch Set 10: Code-Review+2 (1 comment) File src/soc/amd/cezanne/include/soc/acpi.h: PS10: Note: This empty header is needed because soc/amd/common/block/lpc/lpc.c includes it. -- To view, visit https://review.coreboot.org/c/coreboot/+/49929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Gerrit-Change-Number: 49929 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Tue, 09 Feb 2021 10:10:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/stack-test test case
by Name of user not set (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Martin Roth, Paul Fagerburg, Jan Dabros. jacz(a)semihalf.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50305 ) Change subject: tests: Add lib/stack-test test case ...................................................................... Patch Set 2: (1 comment) File tests/lib/stack-test.c: https://review.coreboot.org/c/coreboot/+/50305/comment/f3829a35_b29d5c48 PS1, Line 102: stack[i] = 0x42420707; > > the stack should have even size […] I do not think that size being even or odd changes anything in this situation. A stack with an even number of bytes is common as its length is aligned to CPU word size (or related value), thus should not have an odd size. What are your thoughts on this matter? Should I really change it back? -- To view, visit https://review.coreboot.org/c/coreboot/+/50305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 Gerrit-Change-Number: 50305 Gerrit-PatchSet: 2 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 09:56:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: jacz(a)semihalf.com Comment-In-Reply-To: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Kyösti Mälkki, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50415 ) Change subject: soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779 Gerrit-Change-Number: 50415 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Feb 2021 09:39:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz
by Sam McNally (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Kevin Chiu, Martin Roth, Furquan Shaikh, Kangheui Won, Bhanu Prakash Maiya. Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50420 ) Change subject: mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5 Gerrit-Change-Number: 50420 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 09:29:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz
by Kevin Chiu (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Sam McNally, Martin Roth, Furquan Shaikh, Kangheui Won, Bhanu Prakash Maiya. Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50420 ) Change subject: mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50420/comment/925e2c1f_95ae9ca3 PS1, Line 12: master > zork Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5 Gerrit-Change-Number: 50420 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 09:29:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sam McNally <sammc(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021