coreboot-gerrit February 2021

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Change in coreboot[master]: sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER`
by Michał Żygowski (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50424 ) Change subject: sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69 Gerrit-Change-Number: 50424 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 11:49:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Michał Żygowski. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50423 ) Change subject: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > We have those BIT macros elsewhere right? Yes. They're not used anywhere in this file, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/50423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759bdef44f7ca0f35350901998f6820820005b38 Gerrit-Change-Number: 50423 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 11:37:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/variants/vilboz: Disable ASPM L1.2 for SD card reader
by EricR Lai (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: John Su, Shirley Her, Martin Roth, Furquan Shaikh, Victor Ding, Dtrain Hsu, Rob Barnes, chris wang. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50280 ) Change subject: mb/google/zork/variants/vilboz: Disable ASPM L1.2 for SD card reader ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Wait the feedback if we need to turn off L1.2 for all Zork. -- To view, visit https://review.coreboot.org/c/coreboot/+/50280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f24c08411eabb1579c76aaafbe3eb054db54f69 Gerrit-Change-Number: 50280 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Shirley Her <shirley.her(a)bayhubtech.corp-partner.google.com> Gerrit-Reviewer: Victor Ding <victording(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Shirley Her <shirley.her(a)bayhubtech.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Victor Ding <victording(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 11:36:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] soc/intel/cannonlake: Enable EIST for all boards
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50427 ) Change subject: [RFC] soc/intel/cannonlake: Enable EIST for all boards ...................................................................... [RFC] soc/intel/cannonlake: Enable EIST for all boards Invert the `eist_enabled` option and do not set it anywhere. Can we do this? Does any board require EIST to be disabled? Change-Id: Iae5dd655eca36779db89929c0020b994e69e0f8d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c 8 files changed, 3 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/50427/1 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 4a93065..6fe8b89 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -19,9 +19,6 @@ .tdp_pl2_override = 30, }" - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" #register "enable_c6dram" = "1" diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 4d35c47..d38a62f 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -134,9 +134,6 @@ # Disable S0ix register "s0ix_enable" = "0" - # Enable Turbo - register "eist_enable" = "1" - register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 8fb84ce..b9865db 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -11,9 +11,6 @@ .tdp_pl2_override = 28, }" - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_FixedHigh" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 3a0758a..dcb8b7d 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -19,9 +19,6 @@ .tdp_pl2_override = 30, }" - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" #register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 6cf5c94..1a8767d 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -16,9 +16,6 @@ .tdp_pl2_override = 78, }" - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 5b09b48..a9c5ab9 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -142,7 +142,7 @@ config_t *config = config_of_soc(); /* Generate P-state tables */ - if (config->eist_enable) + if (!config->eist_disable) generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 15592d5..685714a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -230,8 +230,7 @@ * 11b - Reserved */ uint8_t SendVrMbxCmd; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable; /* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 6a4f773..d8f5cf7 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -37,7 +37,7 @@ wrmsr(IA32_MISC_ENABLE, msr); /* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable); /* Disable Thermal interrupts */ msr.lo = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/50427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae5dd655eca36779db89929c0020b994e69e0f8d Gerrit-Change-Number: 50427 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled`
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50426 ) Change subject: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled` ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I noticed that `eist_enable` isn't set for any board using these platforms. Is this intentional? Can we flip the default, and only disable EIST on boards that actually need it because of e.g. thermal/power constraints? -- To view, visit https://review.coreboot.org/c/coreboot/+/50426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I313194edb3795962a42eebde9683579abc078851 Gerrit-Change-Number: 50426 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 11:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled`
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50426 ) Change subject: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled` ...................................................................... [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled` This enables EIST and P states by default for all boards using these platforms. Change-Id: I313194edb3795962a42eebde9683579abc078851 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/cpu.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/cpu.c 15 files changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/50426/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1536de1..fc16e90 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -141,7 +141,7 @@ { config_t *config = config_of_soc(); - if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 13e77cf..f049c0c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -154,8 +154,7 @@ /* PL2 Override value in Watts */ uint32_t tdp_pl2_override; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable; /* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 32f5ea2..4e8255f 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -41,7 +41,7 @@ wrmsr(IA32_MISC_ENABLE, msr); /* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 0c87cfd..2850944 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -140,7 +140,7 @@ { config_t *config = config_of_soc(); - if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 1d97b36..5be010d 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -137,8 +137,7 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable; /* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 984f7f2..fd6273c 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -35,7 +35,7 @@ wrmsr(IA32_MISC_ENABLE, msr); /* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 6240f68..cd62cc1 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -137,7 +137,7 @@ { config_t *config = config_of_soc(); - if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 64bc70b..634c73c 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -145,8 +145,7 @@ * 11b - Reserved */ uint8_t SendVrMbxCmd; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable; /* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index dd70c85..6e74574 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -35,7 +35,7 @@ wrmsr(IA32_MISC_ENABLE, msr); /* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 1a9286a..84a6ac1 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -140,7 +140,7 @@ { config_t *config = config_of_soc(); - if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 6e52efd..0a10e6f 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -137,8 +137,7 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable; /* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index a3790e1..52fe072 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -35,7 +35,7 @@ wrmsr(IA32_MISC_ENABLE, msr); /* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index d81efb9..814a78e 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -140,7 +140,7 @@ { config_t *config = config_of_soc(); - if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index edc7160..7eb34f1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -271,8 +271,7 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable; /* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 974401f..a38f3ce 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -41,7 +41,7 @@ wrmsr(IA32_MISC_ENABLE, msr); /* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable); /* Disable Thermal interrupts */ msr.lo = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/50426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I313194edb3795962a42eebde9683579abc078851 Gerrit-Change-Number: 50426 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros
by Michał Żygowski (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Angel Pons, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50423 ) Change subject: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: We have those BIT macros elsewhere right? -- To view, visit https://review.coreboot.org/c/coreboot/+/50423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759bdef44f7ca0f35350901998f6820820005b38 Gerrit-Change-Number: 50423 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 11:17:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/amd/pi/hudson/pci.c: Remove empty init operation
by Michał Żygowski (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Angel Pons, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50422 ) Change subject: sb/amd/pi/hudson/pci.c: Remove empty init operation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51 Gerrit-Change-Number: 50422 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 11:17:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/amd/pi/hudson/imc.c: Remove duplicated comment
by Michał Żygowski (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Angel Pons, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50421 ) Change subject: sb/amd/pi/hudson/imc.c: Remove duplicated comment ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce Gerrit-Change-Number: 50421 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 11:16:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50425 ) Change subject: sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments ...................................................................... sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/50425/1 diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 16904f1..20c15f0 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -28,9 +28,9 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1 Gerrit-Change-Number: 50425 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021