coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/common/block/acpi/pm_state: don't rely on undefined behavior
by Marshall Dawson (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50492 ) Change subject: soc/amd/common/block/acpi/pm_state: don't rely on undefined behavior ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a76a38f8d84666f6b9c0bfffecca064fa82d593 Gerrit-Change-Number: 50492 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 17:38:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: 3rdparty/intel-microcode: Update to 20200616 release
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Marc Jones. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50553 ) Change subject: 3rdparty/intel-microcode: Update to 20200616 release ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Ic010594a59b692b18eb40656c283c080c34c4d2c Gerrit-Change-Number: 50553 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 17:38:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: 3rdparty/intel-microcode: Update to 20200616 release
by Marc Jones (Code Review) 11 Feb '21

11 Feb '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50553 ) Change subject: 3rdparty/intel-microcode: Update to 20200616 release ...................................................................... 3rdparty/intel-microcode: Update to 20200616 release Update the 4.11_branch to the 20200616 intel microcde release. Change-Id: Ic010594a59b692b18eb40656c283c080c34c4d2c Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M 3rdparty/intel-microcode 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/50553/1 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 1dd14da..0e4288f 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 1dd14da6d1ea5cfbd95923653f31c04aac3aa655 +Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 -- To view, visit https://review.coreboot.org/c/coreboot/+/50553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Ic010594a59b692b18eb40656c283c080c34c4d2c Gerrit-Change-Number: 50553 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/shuboz: Adjust GPIO settings
by Martin Roth (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Bhanu Prakash Maiya, Kane Chen. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50277 ) Change subject: mb/google/zork/var/shuboz: Adjust GPIO settings ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/zork/variants/shuboz/gpio.c: https://review.coreboot.org/c/coreboot/+/50277/comment/039bbb9f_bb255c0f PS2, Line 14: /* RAM ID 2 */ : PAD_GPI(GPIO_86, PULL_NONE), > RAM ID should be pulled up/down by external resistor. yes, but it's a weak pull up/down. We definitely want this GPIO left as an output set high for runtime. http://issuetracker.google.com/179333669#comment2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b Gerrit-Change-Number: 50277 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 17:12:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/fch: remove comment about ForceStpClkRetry
by Martin Roth (Code Review) 11 Feb '21

11 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50495 ) Change subject: soc/amd/picasso/fch: remove comment about ForceStpClkRetry ...................................................................... soc/amd/picasso/fch: remove comment about ForceStpClkRetry The corresponding bit is marked as reserved in the PPR. Also there's no BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also fix the style of the comment. Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50495 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/fch.c 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 5d62e8e..e52090a 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -135,9 +135,7 @@ configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); /* SMI on SlpTyp requires sending SMI before completion - * response of the I/O write. The BKDG also specifies - * clearing ForceStpClkRetry for SMI trapping. - */ + response of the I/O write. */ reg = pm_read32(PM_PCI_CTRL); reg |= FORCE_SLPSTATE_RETRY; pm_write32(PM_PCI_CTRL, reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/50495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc Gerrit-Change-Number: 50495 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/amd/fsp/picasso: increase FSPS UPD block size
by Nikolai Vyssotski (Code Review) 11 Feb '21

11 Feb '21

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50552 ) Change subject: vc/amd/fsp/picasso: increase FSPS UPD block size ...................................................................... vc/amd/fsp/picasso: increase FSPS UPD block size We will need more FSPS UPD space for PEI GOP changes coming BUG=b:171234996 BRANCH=Zork Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/50552/1 diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index f931bf0..8f258f3 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -65,8 +65,8 @@ /** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x; /** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x; /** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x; - /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3]; - /** Offset 0x0150**/ uint16_t UpdTerminator; + /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[51]; + /** Offset 0x0180**/ uint16_t UpdTerminator; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/50552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07 Gerrit-Change-Number: 50552 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*: Move prmrr_core_configure
by Tim Wawrzynczak (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Patrick Rudolph, Subrata Banik, Andrey Petrov. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49898 ) Change subject: soc/intel/*: Move prmrr_core_configure ...................................................................... Patch Set 8: Code-Review+2 (1 comment) Patchset: PS8: All I see is: "After caching is enabled and MTRR/PRMRR are properly configured, the BIOS is required to reload the microcode update on all threads in order to activate certain SGX." -- To view, visit https://review.coreboot.org/c/coreboot/+/49898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf Gerrit-Change-Number: 49898 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 16:49:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/amd/common: add and use fch_enable_ioapic_decode
by Marshall Dawson (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50513 ) Change subject: [UNTESTED] soc/amd/common: add and use fch_enable_ioapic_decode ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Gerrit-Change-Number: 50513 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 16:49:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init
by Tim Wawrzynczak (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Subrata Banik, Michael Niewöhner, Andrey Petrov, Nathaniel L Desimone. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 ) Change subject: soc/intel/*: Update microcode as specified for MP-init ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/49899/comment/98232514_233ec0dd PS13, Line 70: PRMRR > > PRMRR isn't currently configured on those platforms, so a second microcode update isn't required a […] Well, if we're not passing MicrocodeRegionBase to the FSP, then the 2nd reload won't be done by the FSP; ADL is the only platform that currently does it; I think Michael is right, it seems like the 2nd reload is mostly for setting PRMRRs, which are used by SGX & C6DRAM, so if those options are selected, I think the 2nd reload is required. -- To view, visit https://review.coreboot.org/c/coreboot/+/49899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf2b009ac9dd7cd462abe0f787f27b09feb6ec5b Gerrit-Change-Number: 49899 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 16:49:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Fix missing header in amd_pci_utils.h
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50508 ) Change subject: soc/amd/common: Fix missing header in amd_pci_utils.h ...................................................................... soc/amd/common: Fix missing header in amd_pci_utils.h This was causing a build error because size_t wasn't defined. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50508 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 46fcfbf..a14aecf 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -3,7 +3,7 @@ #ifndef AMD_BLOCK_PCI_UTIL_H #define AMD_BLOCK_PCI_UTIL_H -#include <stdint.h> +#include <types.h> #include <soc/amd_pci_int_defs.h> /* FCH index/data registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7 Gerrit-Change-Number: 50508 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit February 2021