coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/cezanne/smihandler: add psp_notify_smm call
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50537 to look at the new patch set (#2). Change subject: soc/amd/cezanne/smihandler: add psp_notify_smm call ...................................................................... soc/amd/cezanne/smihandler: add psp_notify_smm call TEST=Majolica still gets to SeaBIOS. Like before this patch the PSP still has the recovery flag set in its return value, but we likely still miss some PSP initialization in FSP. Change-Id: I9f343452ef2ea6b01f9b2fd0cf6371218d046046 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/smihandler.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/50537/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f343452ef2ea6b01f9b2fd0cf6371218d046046 Gerrit-Change-Number: 50537 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd: Move southbridge_write_acpi_tables
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Angel Pons, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50509 ) Change subject: soc/amd: Move southbridge_write_acpi_tables ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/acpi/tables.c: PS1: > nit: rename to `acpi_tables. […] It's already under the acpi directory, so acpi/acpi_tables.c seems redundant don't you agree? -- To view, visit https://review.coreboot.org/c/coreboot/+/50509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0 Gerrit-Change-Number: 50509 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 16:23:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50488 ) Change subject: soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler ...................................................................... soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler Only the ACPI enable/disable functionality is implemented and sleep is also not implemented yet. This will be added in future patches. Change-Id: I7701944023ce2e86586679c32c4138d4488768a1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50488 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/smihandler.c 1 file changed, 76 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 46164e4..80dbb7b 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -1,14 +1,90 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> #include <amdblocks/smm.h> +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> #include <cpu/x86/smm.h> +#include <soc/smi.h> +#include <types.h> + +static void fch_apmc_smi_handler(void) +{ + const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); + + switch (cmd) { + case APM_CNT_ACPI_ENABLE: + acpi_enable_sci(); + break; + case APM_CNT_ACPI_DISABLE: + acpi_disable_sci(); + } + + mainboard_smi_apmc(cmd); +} + +static void fch_slp_typ_handler(void) +{ + uint16_t pm1cnt; + uint8_t slp_typ; + + /* Figure out SLP_TYP */ + pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); + slp_typ = acpi_sleep_from_pm1(pm1cnt); + + /* Do any mainboard sleep handling */ + mainboard_smi_sleep(slp_typ); + + switch (slp_typ) { + case ACPI_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case ACPI_S3: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + break; + case ACPI_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case ACPI_S5: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; + } + + if (slp_typ >= ACPI_S3) { + printk(BIOS_ERR, "Error: System did not go to sleep\n"); + hlt(); + } +} int southbridge_io_trap_handler(int smif) { return 0; } +/* + * Table of functions supported in the SMI handler. Note that SMI source setup + * in fch.c is unrelated to this list. + */ +static const struct smi_sources_t smi_sources[] = { + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +}; + void *get_smi_source_handler(int source) { + size_t i; + + for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) + if (smi_sources[i].type == source) + return smi_sources[i].handler; + return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7701944023ce2e86586679c32c4138d4488768a1 Gerrit-Change-Number: 50488 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: select soc-specific ACPI functionality
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50487 ) Change subject: soc/amd/cezanne: select soc-specific ACPI functionality ...................................................................... soc/amd/cezanne: select soc-specific ACPI functionality This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be generated for now. There's also no globalnvs.asl that corresponds to nvs.h yet. The added nvs.h has some currently unused fields, but still having them in the struct aligns it with Picasso and also might reduce the noise in future ACPI patches a bit. When most of the ACPI code for Cezanne has landed, we need to do a cleanup though. Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50487 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/include/soc/nvs.h M src/soc/amd/cezanne/include/soc/southbridge.h 3 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 2de60d7..cfdf6ff 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,6 +13,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select ACPI_AMD_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -23,6 +24,7 @@ select PLATFORM_USES_FSP2_0 select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h new file mode 100644 index 0000000..7eb6cf6 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/nvs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * NOTE: The layout of the global_nvs structure below must match the layout + * in soc/soc/amd/cezanne/acpi/globalnvs.asl !!! + * + */ + +#ifndef AMD_CEZANNE_NVS_H +#define AMD_CEZANNE_NVS_H + +#include <stdint.h> + +struct __packed global_nvs { + /* Miscellaneous */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ + uint8_t lids; /* 0x01 - LID State */ + uint8_t pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ +}; + +#endif /* AMD_CEZANNE_NVS_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index dcb5ef1..0b5882e 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -59,6 +59,10 @@ #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ /* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Gerrit-Change-Number: 50487 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*/smihandler: use size_t and unsigned int
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50486 ) Change subject: soc/amd/*/smihandler: use size_t and unsigned int ...................................................................... soc/amd/*/smihandler: use size_t and unsigned int signed int should only be used when we need negative values and in those cases the value shouldn't became negative. Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 2 files changed, 6 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 735fd77..d478aad 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -18,6 +18,7 @@ #include <amdblocks/smm.h> #include <elog.h> #include <soc/smu.h> +#include <types.h> /* bits in smm_io_trap */ #define SMM_IO_TRAP_PORT_OFFSET 16 @@ -33,7 +34,7 @@ static void *find_save_state(int cmd) { - int core; + unsigned int core; amd64_smm_state_save_area_t *state; u32 smm_io_trap; u8 reg_al; @@ -225,7 +226,7 @@ void *get_smi_source_handler(int source) { - int i; + size_t i; for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) if (smi_sources[i].type == source) diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 3a65f55..23951b2 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -16,6 +16,7 @@ #include <amdblocks/smi.h> #include <amdblocks/smm.h> #include <elog.h> +#include <types.h> /* bits in smm_io_trap */ #define SMM_IO_TRAP_PORT_OFFSET 16 @@ -31,7 +32,7 @@ static void *find_save_state(int cmd) { - int core; + unsigned int core; amd64_smm_state_save_area_t *state; u32 smm_io_trap; u8 reg_al; @@ -220,7 +221,7 @@ void *get_smi_source_handler(int source) { - int i; + size_t i; for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) if (smi_sources[i].type == source) -- To view, visit https://review.coreboot.org/c/coreboot/+/50486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Gerrit-Change-Number: 50486 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Add PCI IRQ Router definitions
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50451 ) Change subject: soc/amd/cezanne: Add PCI IRQ Router definitions ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50451/comment/013b1095_fa9aff95 PS2, Line 10: I renamed Misc1 and Misc2 to HPET_L and HPET_H. > I'm struggling to find anything in the PPR to support this. […] IOx00C01_x0A [Intr_Misc1Map] (FCH::IO::IntrMisc1Map) 7:0 HPET. Read-write. Reset: 00h. Writes to this register update the bits in FCH::TMR::HPET::TMR0_CONF_CAP_H [7:0], FCH::TMR::HPET::TMR1_CONF_CAP_H [7:0] and FCH::TMR::HPET::TMR2_CONF_CAP_H [7:0]; IOx00C01_x0B [Intr_Misc2Map] (FCH::IO::IntrMisc2Map) HPET. Read-write. Reset: 00h. Writes to this register update this bits in FCH::TMR::HPET::TMR0_CONF_CAP_H [15:8], FCH::TMR::HPET::TMR1_CONF_CAP_H [15:8] and FCH::TMR::HPET::TMR2_CONF_CAP_H [15:8]; HPETx00000104 (FCH::TMR::HPET::TMR0_CONF_CAP_H) 31:0 tmrintroutecap. Read-only. Reset: 00C0_0000h. Indicates which INT entry of IoAPIC can be assigned to the timer interrupt. Read only. I never knew how the HPET was configured to route interrupts until I actually read the Misc descriptions. Should I rename HPET_X to something else? File src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h: https://review.coreboot.org/c/coreboot/+/50451/comment/946e85ce_0aa4545a PS1, Line 61: #define PIRQ_UART2 0x78 /* UART2 */ : #define PIRQ_UART3 0x79 /* UART3 */ > By don't exist, do you perhaps mean that they're not pinned out for FP6 and are made unavailable? ( […] There are only 2 UARTs on the device: UARTx[A:9]000 I can mark these as reserved if you have sent a request to update the PPR. -- To view, visit https://review.coreboot.org/c/coreboot/+/50451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e Gerrit-Change-Number: 50451 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 16:17:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/smihandler: remove replace southbridge references with fch
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50485 ) Change subject: soc/amd/*/smihandler: remove replace southbridge references with fch ...................................................................... soc/amd/*/smihandler: remove replace southbridge references with fch Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50485 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 2 files changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 928669d..735fd77 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -97,7 +97,7 @@ io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); } -static void sb_apmc_smi_handler(void) +static void fch_apmc_smi_handler(void) { const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); @@ -124,7 +124,7 @@ mainboard_smi_apmc(cmd); } -static void sb_slp_typ_handler(void) +static void fch_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; uint16_t pm1cnt, reg16; @@ -219,8 +219,8 @@ * in fch.c is unrelated to this list. */ static const struct smi_sources_t smi_sources[] = { - { .type = SMITYPE_SMI_CMD_PORT, .handler = sb_apmc_smi_handler }, - { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, }; void *get_smi_source_handler(int source) diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 0b0f5c1..3a65f55 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -95,7 +95,7 @@ io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); } -static void sb_apmc_smi_handler(void) +static void fch_apmc_smi_handler(void) { const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); @@ -119,7 +119,7 @@ mainboard_smi_apmc(cmd); } -static void sb_slp_typ_handler(void) +static void fch_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; uint16_t pm1cnt, reg16; @@ -214,8 +214,8 @@ * in southbridge.c is unrelated to this list. */ static const struct smi_sources_t smi_sources[] = { - { .type = SMITYPE_SMI_CMD_PORT, .handler = sb_apmc_smi_handler }, - { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, }; void *get_smi_source_handler(int source) -- To view, visit https://review.coreboot.org/c/coreboot/+/50485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32 Gerrit-Change-Number: 50485 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/chip: set device operations for UART MMIO devices
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50484 ) Change subject: soc/amd/cezanne/chip: set device operations for UART MMIO devices ...................................................................... soc/amd/cezanne/chip: set device operations for UART MMIO devices Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50484 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/chip.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 6e4df42..ffd56de 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -6,6 +6,9 @@ #include <types.h> #include "chip.h" +/* Supplied by uart.c */ +extern struct device_operations cezanne_uart_mmio_ops; + struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, @@ -20,6 +23,12 @@ static void set_mmio_dev_ops(struct device *dev) { + switch (dev->path.mmio.addr) { + case APU_UART0_BASE: + case APU_UART1_BASE: + dev->ops = &cezanne_uart_mmio_ops; + break; + } } static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/50484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc Gerrit-Change-Number: 50484 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: add empty mp_init_cpus
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50483 ) Change subject: soc/amd/cezanne: add empty mp_init_cpus ...................................................................... soc/amd/cezanne: add empty mp_init_cpus Change-Id: I845a7e2cfea58ca08cd2a6f0d884dbbbe1a7bdef Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50483 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/cpu.c 2 files changed, 7 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 4aac2ec..6e4df42 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -7,8 +7,9 @@ #include "chip.h" struct device_operations cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = mp_cpu_bus_init, }; static struct device_operations pci_domain_ops = { diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index cd2d6ed..b199d99 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -7,6 +7,10 @@ #include <device/device.h> #include <soc/cpu.h> +void mp_init_cpus(struct bus *cpu_bus) +{ +} + static void zen_2_3_init(struct device *dev) { setup_lapic(); -- To view, visit https://review.coreboot.org/c/coreboot/+/50483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I845a7e2cfea58ca08cd2a6f0d884dbbbe1a7bdef Gerrit-Change-Number: 50483 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/cpu: add basic zen_2_3_init functionality
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50482 ) Change subject: soc/amd/cezanne/cpu: add basic zen_2_3_init functionality ...................................................................... soc/amd/cezanne/cpu: add basic zen_2_3_init functionality The MCA MSRs aren't getting cleared and no microcode update gets applied for now. Both will be added later. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50482 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/cpu.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 3e0a7db..cd2d6ed 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -1,12 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/cpu.h> #include <console/console.h> #include <cpu/cpu.h> +#include <cpu/x86/lapic.h> #include <device/device.h> #include <soc/cpu.h> static void zen_2_3_init(struct device *dev) { + setup_lapic(); + set_cstate_io_addr(); } static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/50482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8 Gerrit-Change-Number: 50482 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit February 2021