coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/common: add and use fch_enable_ioapic_decode
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50513 to look at the new patch set (#2). Change subject: soc/amd/common: add and use fch_enable_ioapic_decode ...................................................................... soc/amd/common: add and use fch_enable_ioapic_decode The default value of this bit is 0, so set it right before calling setup_ioapic to make sure that it's set and not to have to rely on FSP doing the right thing. Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/smbus/sm.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/50513/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Gerrit-Change-Number: 50513 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd: add and use fch_enable_hpet_decode
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50512 to look at the new patch set (#2). Change subject: soc/amd: add and use fch_enable_hpet_decode ...................................................................... soc/amd: add and use fch_enable_hpet_decode On Picasso we missed setting this bit in coreboot and since the default after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge and Cezanne have the HPET decode enable bit in the same position in the same register. In the ACPI table entry written by southbridge_write_acpi_tables the HPET entry gets added, so we should make sure that we enable the decode. TEST=HPET still works on Mandolin. Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/50512/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Gerrit-Change-Number: 50512 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/acpi: Add missing <types.h>
by HAOUAS Elyes (Code Review) 11 Feb '21

11 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50555 ) Change subject: src/acpi: Add missing <types.h> ...................................................................... src/acpi: Add missing <types.h> Change-Id: Iec78183b43ea26d9de14e0ce28eef6fc0361cc95 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/acpi/acpigen.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/50555/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index fc13689..867e163 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -23,6 +23,7 @@ #include <commonlib/helpers.h> #include <cpu/cpu.h> #include <cbfs.h> +#include <types.h> #include <version.h> #include <commonlib/sort.h> diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 5cc6a4e..4d9395f 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -21,6 +21,7 @@ #include <device/pci_def.h> #include <device/pci_type.h> #include <device/soundwire.h> +#include <types.h> static char *gencurrent; -- To view, visit https://review.coreboot.org/c/coreboot/+/50555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec78183b43ea26d9de14e0ce28eef6fc0361cc95 Gerrit-Change-Number: 50555 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Enable CONFIG_CHROEMOS
by Mathew King (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth, Mathew King. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50507 to look at the new patch set (#4). Change subject: mb/google/guybrush: Enable CONFIG_CHROEMOS ...................................................................... mb/google/guybrush: Enable CONFIG_CHROEMOS BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk(a)chromium.org> Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/Makefile.inc A src/mainboard/google/guybrush/chromeos.c 3 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/50507/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 Gerrit-Change-Number: 50507 Gerrit-PatchSet: 4 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Enable CONFIG_CHROEMOS
by Mathew King (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50507 to look at the new patch set (#3). Change subject: mb/google/guybrush: Enable CONFIG_CHROEMOS ...................................................................... mb/google/guybrush: Enable CONFIG_CHROEMOS BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk(a)chromium.org> Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/Makefile.inc A src/mainboard/google/guybrush/chromeos.c 3 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/50507/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 Gerrit-Change-Number: 50507 Gerrit-PatchSet: 3 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: trogdor: Add fingerprint power sequencing
by mturney mturney (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50504 ) Change subject: trogdor: Add fingerprint power sequencing ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea Gerrit-Change-Number: 50504 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 18:14:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable CONFIG_CHROEMOS
by Mathew King (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50507 to look at the new patch set (#2). Change subject: mb/google/guybrush: Enable CONFIG_CHROEMOS ...................................................................... mb/google/guybrush: Enable CONFIG_CHROEMOS BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk(a)chromium.org> Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/Makefile.inc A src/mainboard/google/guybrush/chromeos.c 3 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/50507/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 Gerrit-Change-Number: 50507 Gerrit-PatchSet: 2 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Second pass GPIO configuration
by Mathew King (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Raul Rangel, Martin Roth, EricR Lai, Karthik Ramasubramanian, Felix Held. Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50450 ) Change subject: mb/google/guybrush: Second pass GPIO configuration ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > @Mat, do you based 0210 or 0209 schematic? I mainly used the GPIO planning spreadsheet. -- To view, visit https://review.coreboot.org/c/coreboot/+/50450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602 Gerrit-Change-Number: 50450 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 18:06:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/i945: Use u8, unsigned int and size_t
by HAOUAS Elyes (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50554 ) Change subject: nb/intel/i945: Use u8, unsigned int and size_t ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/50554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2688d67c0421581344df1975df739e587a5c095c Gerrit-Change-Number: 50554 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 18:03:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/i945: Use u8, unsigned int and size_t
by HAOUAS Elyes (Code Review) 11 Feb '21

11 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50554 ) Change subject: nb/intel/i945: Use u8, unsigned int and size_t ...................................................................... nb/intel/i945: Use u8, unsigned int and size_t The values are not negative. Change-Id: I2688d67c0421581344df1975df739e587a5c095c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/rcven.c 5 files changed, 42 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50554/1 diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index db987ca..64ba33c 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -26,7 +26,7 @@ void dump_pci_device(unsigned int dev) { - int i; + unsigned int i; printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); @@ -63,7 +63,7 @@ device = DIMM0; while (device <= DIMM3) { int status = 0; - int i; + unsigned int i; printk(BIOS_DEBUG, "\ndimm %02x", device); for (i = 0; (i < 256); i++) { diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b91afda..b4aaaac 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -327,7 +327,7 @@ { u32 reg32; u32 timeout; - int activate_aspm = 1; /* hardcode ASPM for now */ + unsigned int activate_aspm = 1; /* hardcode ASPM for now */ printk(BIOS_DEBUG, "Setting up DMI RCRB\n"); @@ -656,7 +656,7 @@ 0xf60, 0xf74, 0xf88, 0xf9c, 0xfb0, 0xfc4, 0xfd8, 0xfec }; - int i; + size_t i; for (i = 0; i < ARRAY_SIZE(reglist); i++) pci_update_config32(p2peg, reglist[i], ~(0xf << 28), 2 << 28); } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b396eff..788e34f 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -375,7 +375,7 @@ unsigned int pphysbase, unsigned int piobase, u8 *mmiobase, unsigned int pgfx) { - int i; + unsigned int i; u32 hactive, vactive; u16 reg16; u32 uma_size; @@ -544,7 +544,7 @@ /* if vga is not connected it should have a correct header */ static int probe_edid(u8 *mmiobase, u8 slave) { - int i; + unsigned int i; u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(mmiobase + GMBUS0, slave, 0x50, vga_edid, 128); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a1a9a9c..a392b26 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -79,7 +79,7 @@ void sdram_dump_mchbar_registers(void) { - int i; + unsigned int i; printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n"); for (i = 0; i < 0xfff; i += 4) { @@ -91,7 +91,7 @@ static int memclk(void) { - int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; + unsigned int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { case 1: return 400; @@ -287,7 +287,7 @@ static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved_timings) { - int i, j; + unsigned int i, j; u8 raw_spd[SPD_SIZE_MAX_DDR2]; u8 dimm_mask = 0; @@ -463,7 +463,7 @@ static void choose_tclk(struct sys_info *sysinfo, struct timings *saved_timings) { u32 ctrl_min_tclk; - int try_cas; + u8 try_cas; ctrl_min_tclk = 2 * 256 * 1000 / sdram_capabilities_max_supported_memory_frequency(); normalize_tck(&ctrl_min_tclk); @@ -575,7 +575,7 @@ static void sdram_program_dram_width(struct sys_info *sysinfo) { u16 c0dramw = 0, c1dramw = 0; - int i, idx; + unsigned int i, idx; if (sysinfo->dual_channel) idx = 2; @@ -627,7 +627,7 @@ static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table) { - int i; + unsigned int i; for (i = 0; i < 16; i++) MCHBAR32(offset+(i * 4)) = slew_rate_table[i]; @@ -762,7 +762,7 @@ DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210 }; -static const u32 *slew_group_lookup(int dual_channel, int index) +static const u32 *slew_group_lookup(u8 dual_channel, int index) { const u8 *slew_group; /* Dual Channel needs different tables. */ @@ -899,7 +899,7 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) { const u8 *strength_multiplier; - int idx, dual_channel; + u8 idx, dual_channel; /* Set Strength Multipliers */ @@ -964,7 +964,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) { u32 channeldll = 0; - int i; + unsigned int i; printk(BIOS_DEBUG, "Programming DLL Timings...\n"); @@ -1137,8 +1137,8 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) { - int i; - int cum0, cum1, tolud, tom, pci_mmio_size; + unsigned int i; + size_t cum0, cum1, tolud, tom, pci_mmio_size; const struct device *dev; const struct northbridge_intel_i945_config *cfg = NULL; @@ -1197,7 +1197,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo) { - int i; + unsigned int i; u16 dra0 = 0, dra1 = 0, dra = 0; printk(BIOS_DEBUG, "Setting row attributes...\n"); @@ -1251,7 +1251,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo) { u32 off32; - int i; + unsigned int i; MCHBAR16(C1BNKARC) &= 0xff00; MCHBAR16(C0BNKARC) &= 0xff00; @@ -1296,7 +1296,7 @@ static void sdram_program_cke_tristate(struct sys_info *sysinfo) { u32 reg32; - int i; + unsigned int i; reg32 = MCHBAR32(C0DRC1); @@ -1327,7 +1327,7 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo) { u32 reg32; - int i; + unsigned int i; reg32 = MCHBAR32(C0DRC2); @@ -1348,10 +1348,11 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) { - u32 reg32, tRD_min; + u32 reg32; + u8 tRD_min; u32 tWTR; u32 temp_drt; - int i, page_size; + unsigned int i, page_size; static const u8 cas_table[] = { 2, 1, 0, 3 @@ -1808,7 +1809,7 @@ static void sdram_program_clock_crossing(void) { - int idx = 0; + unsigned int idx = 0; /** * We add the indices according to our clocks from CLKCFG. @@ -2121,8 +2122,8 @@ { u16 reg16; u32 reg32; - int integrated_graphics = 1; - int i; + unsigned int integrated_graphics = 1; + unsigned int i; reg32 = MCHBAR32(C0DRT2); reg32 &= 0xffffff00; @@ -2304,7 +2305,7 @@ static void sdram_save_receive_enable(void) { - int i; + unsigned int i; u32 reg32; u8 values[4]; @@ -2339,7 +2340,7 @@ static void sdram_recover_receive_enable(void) { - int i; + unsigned int i; u32 reg32; u8 values[4]; @@ -2397,7 +2398,7 @@ }; u32 reg32; - int cas; + u8 cas; reg32 = MCHBAR32(ODTC); reg32 &= ~(3 << 16); @@ -2496,7 +2497,8 @@ static void sdram_jedec_enable(struct sys_info *sysinfo) { - int i, nonzero; + unsigned int i; + int nonzero; u32 bankaddr = 0, tmpaddr, mrsaddr = 0; for (i = 0, nonzero = -1; i < 8; i++) { diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 0b58904..a9a3834 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -8,10 +8,10 @@ /** * sample the strobes signal */ -static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo) +static u32 sample_strobes(u8 channel_offset, struct sys_info *sysinfo) { u32 reg32, addr; - int i; + unsigned int i; MCHBAR32(C0DRC1 + channel_offset) |= (1 << 6); @@ -47,7 +47,7 @@ * This function sets receive enable coarse and medium timing parameters */ -static void set_receive_enable(int channel_offset, u8 medium, u8 coarse) +static void set_receive_enable(u8 channel_offset, u8 medium, u8 coarse) { u32 reg32; @@ -84,7 +84,7 @@ } -static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine) +static int normalize(u8 channel_offset, u8 *mediumcoarse, u8 *fine) { printk(BIOS_SPEW, " %s()\n", __func__); @@ -106,7 +106,7 @@ return 0; } -static int find_preamble(int channel_offset, u8 *mediumcoarse, +static int find_preamble(u8 channel_offset, u8 *mediumcoarse, struct sys_info *sysinfo) { /* find start of the data phase */ @@ -139,7 +139,7 @@ * add a quarter clock to the current receive enable settings */ -static int add_quarter_clock(int channel_offset, u8 *mediumcoarse, u8 *fine) +static int add_quarter_clock(u8 channel_offset, u8 *mediumcoarse, u8 *fine) { printk(BIOS_SPEW, " %s() mediumcoarse=%02x fine=%02x\n", __func__, *mediumcoarse, *fine); @@ -162,7 +162,7 @@ return 0; } -static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine, +static int find_strobes_low(u8 channel_offset, u8 *mediumcoarse, u8 *fine, struct sys_info *sysinfo) { u32 rcvenmt; @@ -195,11 +195,11 @@ return 0; } -static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine, +static int find_strobes_edge(u8 channel_offset, u8 *mediumcoarse, u8 *fine, struct sys_info *sysinfo) { - int counter; + unsigned int counter; u32 rcvenmt; printk(BIOS_SPEW, " %s()\n", __func__); @@ -258,7 +258,7 @@ * a lot of if ()s so let's just pass 0 or 0x80 for the channel offset. */ -static int receive_enable_autoconfig(int channel_offset, struct sys_info *sysinfo) +static int receive_enable_autoconfig(u8 channel_offset, struct sys_info *sysinfo) { u8 mediumcoarse; u8 fine; -- To view, visit https://review.coreboot.org/c/coreboot/+/50554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2688d67c0421581344df1975df739e587a5c095c Gerrit-Change-Number: 50554 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021