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Change in coreboot[master]: src/arch: Add missing <types.h>
by HAOUAS Elyes (Code Review) 11 Feb '21

11 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50564 ) Change subject: src/arch: Add missing <types.h> ...................................................................... src/arch: Add missing <types.h> Change-Id: I45603a850d50416aef6850e8e65977b0eb9aee6f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/cache.c M src/arch/arm/fit_payload.c M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/fit_payload.c M src/arch/riscv/include/vm.h M src/arch/x86/exception.c M src/arch/x86/memcpy.c M src/arch/x86/memmove.c M src/arch/x86/memset.c M src/arch/x86/postcar_loader.c M src/arch/x86/smbios.c M src/arch/x86/tables.c 13 files changed, 16 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/50564/1 diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index 1c46e04..37ae6d9 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -5,10 +5,9 @@ * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ -#include <stdint.h> - #include <arch/cache.h> #include <program_loading.h> +#include <types.h> void tlb_invalidate_all(void) { diff --git a/src/arch/arm/fit_payload.c b/src/arch/arm/fit_payload.c index 9777e3c..fa8514c 100644 --- a/src/arch/arm/fit_payload.c +++ b/src/arch/arm/fit_payload.c @@ -5,6 +5,7 @@ #include <program_loading.h> #include <fit.h> #include <symbols.h> +#include <types.h> /** * Place the region in free memory range. diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index ae0729e..a220f04 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -5,11 +5,10 @@ * Reference: ARM Architecture Reference Manual, ARMv8-A edition */ -#include <stdint.h> - #include <arch/cache.h> #include <arch/lib_helpers.h> #include <program_loading.h> +#include <types.h> unsigned int dcache_line_bytes(void) { diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 72e5cca..8b5ad6c 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> -#include <stdint.h> #include <string.h> #include <symbols.h> +#include <types.h> #include <console/console.h> #include <arch/mmu.h> diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index c8eba8d..de87548 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -9,6 +9,7 @@ #include <lib.h> #include <fit.h> #include <endian.h> +#include <types.h> #define MAX_KERNEL_SIZE (64*MiB) diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index c1894c7..86686a3 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -4,8 +4,8 @@ #define _VM_H #include <string.h> -#include <stdint.h> #include <arch/encoding.h> +#include <types.h> #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index f10c7bf..b1a7e01 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -7,8 +7,8 @@ #include <console/streams.h> #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> -#include <stdint.h> #include <string.h> +#include <types.h> #if CONFIG(GDB_STUB) diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 1cfdf89..92f1ce0 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <string.h> -#include <stdbool.h> #include <asan.h> +#include <string.h> +#include <types.h> void *memcpy(void *dest, const void *src, size_t n) { diff --git a/src/arch/x86/memmove.c b/src/arch/x86/memmove.c index 3ec50b2..6d34afa 100644 --- a/src/arch/x86/memmove.c +++ b/src/arch/x86/memmove.c @@ -3,9 +3,9 @@ * This file is derived from memcpy_32.c in the Linux kernel. */ -#include <string.h> -#include <stdbool.h> #include <asan.h> +#include <string.h> +#include <types.h> void *memmove(void *dest, const void *src, size_t n) { diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index fc09a9b..8ab18cc 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -2,10 +2,9 @@ /* From glibc-2.14, sysdeps/i386/memset.c */ -#include <string.h> -#include <stdint.h> -#include <stdbool.h> #include <asan.h> +#include <string.h> +#include <types.h> typedef uint32_t op_t; diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index cae5574..6a6dbf2 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -12,6 +12,7 @@ #include <stage_cache.h> #include <timestamp.h> #include <security/vboot/vboot_common.h> +#include <types.h> static inline void stack_push(struct postcar_frame *pcf, uint32_t val) { diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8bc49b1..0100076 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <drivers/vpd/vpd.h> #include <stdlib.h> +#include <types.h> #define update_max(len, max_len, stmt) \ do { \ diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 492674c..3e7f898 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -11,6 +11,7 @@ #include <string.h> #include <cbmem.h> #include <smbios.h> +#include <types.h> static unsigned long write_pirq_table(unsigned long rom_table_end) { -- To view, visit https://review.coreboot.org/c/coreboot/+/50564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45603a850d50416aef6850e8e65977b0eb9aee6f Gerrit-Change-Number: 50564 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Fill FADT and MADT
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50510 ) Change subject: soc/amd/cezanne: Fill FADT and MADT ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50510/comment/1fddf671_8741f645 PS1, Line 9: configure > nit: move to next line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 Gerrit-Change-Number: 50510 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 19:14:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Fill FADT and MADT
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50510 ) Change subject: soc/amd/cezanne: Fill FADT and MADT ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/acpi.c: https://review.coreboot.org/c/coreboot/+/50510/comment/18488902_ac099830 PS1, Line 100: fadt->x_firmware_ctl_h = 0; > I am not actually sure why this is zero'd out. […] I think this came from stoneyridge, which probably came from sb/amd/pi/hudson -- To view, visit https://review.coreboot.org/c/coreboot/+/50510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 Gerrit-Change-Number: 50510 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 19:14:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Second pass GPIO configuration
by Karthik Ramasubramanian (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Raul Rangel, Martin Roth, Mathew King, EricR Lai, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50450 ) Change subject: mb/google/guybrush: Second pass GPIO configuration ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/50450/comment/43111d4e_40be07cb PS1, Line 19: PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), We might need a debounce configuration too. https://review.coreboot.org/c/coreboot/+/50450/comment/90c2d9ff_72040a17 PS1, Line 22: /* EN_PP3300_WLAN */ : PAD_GPO(GPIO_6, LOW), : /* EN_PP3300_TCHPAD */ : PAD_GPO(GPIO_7, LOW), Are we planning to enable these standard components in a subsequent CL or are these enable signals active low? -- To view, visit https://review.coreboot.org/c/coreboot/+/50450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602 Gerrit-Change-Number: 50450 Gerrit-PatchSet: 2 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 19:10:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: drop PWRS from GNVS
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50563 ) Change subject: soc/amd/cezanne: drop PWRS from GNVS ...................................................................... soc/amd/cezanne: drop PWRS from GNVS A copy of Picasso's include/nvs.h was added to Cezanne right before the commit d6ccbb9d48f97dd3bbd4b947fe3bc4857216a363 that removed it for the other mainboards and SoCs, so apply the equivalent change here as well to keep everything in sync. Change-Id: I76b551c05b3c3028a3afb3bc3b77df2401aed7a8 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/include/soc/nvs.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/50563/1 diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h index 7eb6cf6..985798b 100644 --- a/src/soc/amd/cezanne/include/soc/nvs.h +++ b/src/soc/amd/cezanne/include/soc/nvs.h @@ -15,7 +15,7 @@ /* Miscellaneous */ uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t lids; /* 0x01 - LID State */ - uint8_t pwrs; /* 0x02 - AC Power State */ + uint8_t unused_was_pwrs; /* 0x02 - AC Power State */ uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76b551c05b3c3028a3afb3bc3b77df2401aed7a8 Gerrit-Change-Number: 50563 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settings
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

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Change in coreboot[master]: include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50561 ) Change subject: include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS ...................................................................... include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS This is a magic value that means all processors. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic2fc060fda21bec44258bcae62ddb230be542759 --- M src/include/acpi/acpi.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/50561/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 058c0d0..775fc31 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -514,6 +514,8 @@ u8 lint; /* Local APIC LINT# */ } __packed acpi_madt_lapic_nmi_t; +#define ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS 0xff + /* MADT: I/O APIC Structure */ typedef struct acpi_madt_ioapic { u8 type; /* Type (1) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2fc060fda21bec44258bcae62ddb230be542759 Gerrit-Change-Number: 50561 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Add plain dsdt
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Felix Held. Hello Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50560 to review the following change. Change subject: mb/google/guybrush: Add plain dsdt ...................................................................... mb/google/guybrush: Add plain dsdt Needed to enable ACPI support for cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859 --- A src/mainboard/google/guybrush/dsdt.asl 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/50560/1 diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl new file mode 100644 index 0000000..ffe6f40 --- /dev/null +++ b/src/mainboard/google/guybrush/dsdt.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + #include <acpi/dsdt_top.asl> + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + } /* End \_SB scope */ +} +/* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859 Gerrit-Change-Number: 50560 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/majolica: Add plain dsdt
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50559 to review the following change. Change subject: mb/amd/majolica: Add plain dsdt ...................................................................... mb/amd/majolica: Add plain dsdt Needed to enable ACPI support for cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifd71635d3493e0cf104b60ecf94ebdf70d512b94 --- A src/mainboard/amd/majolica/dsdt.asl 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/50559/1 diff --git a/src/mainboard/amd/majolica/dsdt.asl b/src/mainboard/amd/majolica/dsdt.asl new file mode 100644 index 0000000..d84a88b --- /dev/null +++ b/src/mainboard/amd/majolica/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define MAINBOARD_HAS_SPEAKER 1 + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + #include <acpi/dsdt_top.asl> + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + } /* End \_SB scope */ +} +/* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd71635d3493e0cf104b60ecf94ebdf70d512b94 Gerrit-Change-Number: 50559 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Move MADT IRQ override settings into common_config
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50558 ) Change subject: soc/amd: Move MADT IRQ override settings into common_config ...................................................................... soc/amd: Move MADT IRQ override settings into common_config This is another common ACPI setting. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2 --- M src/soc/amd/common/block/acpi/tables.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/block/include/amdblocks/chip.h M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/chip.h 5 files changed, 36 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/50558/1 diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c index f941bc9..88ff252 100644 --- a/src/soc/amd/common/block/acpi/tables.c +++ b/src/soc/amd/common/block/acpi/tables.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <amdblocks/acpi.h> +#include <amdblocks/chip.h> #include <device/device.h> #include <types.h> @@ -23,3 +24,24 @@ return current; } + +unsigned long acpi_fill_madt_irqoverride(unsigned long current) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + unsigned int i; + uint8_t irq; + uint8_t flags; + + for (i = 0; i < ARRAY_SIZE(cfg->irq_override); ++i) { + irq = cfg->irq_override[i].irq; + flags = cfg->irq_override[i].flags; + + if (!flags) + continue; + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, + irq, irq, flags); + } + + return current; +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index badc77b..e6e2520 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -51,4 +51,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); +unsigned long acpi_fill_madt_irqoverride(unsigned long current); + #endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index b365e4d..e18ce64 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -24,6 +24,17 @@ /* Options for these are in src/include/acpi/acpi.h */ uint16_t fadt_boot_arch; uint32_t fadt_flags; + + /** + * IRQ 0 - 15 have a default trigger of edge and default polarity of high. + * If you have a device that requires a different configuration you can override the + * settings here. + */ + struct { + uint8_t irq; + /* See MP_IRQ_* from mpspec.h */ + uint8_t flags; + } irq_override[16]; }; /* diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a6bc97b..8697e79 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -32,11 +32,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - const struct soc_amd_picasso_config *cfg = config_of_soc(); - unsigned int i; - uint8_t irq; - uint8_t flags; - /* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -56,16 +51,7 @@ (acpi_madt_irqoverride_t *)current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); - for (i = 0; i < ARRAY_SIZE(cfg->irq_override); ++i) { - irq = cfg->irq_override[i].irq; - flags = cfg->irq_override[i].flags; - - if (!flags) - continue; - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, - irq, irq, flags); - } + current = acpi_fill_madt_irqoverride(current); /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index a66d77c..549f033 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -120,17 +120,6 @@ /* Enable ACP PME (0 = disable, 1 = enable) */ u8 acp_pme_enable; - /** - * IRQ 0 - 15 have a default trigger of edge and default polarity of high. - * If you have a device that requires a different configuration you can override the - * settings here. - */ - struct { - uint8_t irq; - /* See MP_IRQ_* from mpspec.h */ - uint8_t flags; - } irq_override[16]; - /* System config index */ uint8_t system_config; -- To view, visit https://review.coreboot.org/c/coreboot/+/50558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2 Gerrit-Change-Number: 50558 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021