coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/common: add and use fch_enable_ioapic_decode
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50513 ) Change subject: soc/amd/common: add and use fch_enable_ioapic_decode ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/smbus/sm.c: https://review.coreboot.org/c/coreboot/+/50513/comment/a1d92cb5_25dd1e79 PS2, Line 15: CONFIG_MAX_CPUS > Hrmm, this is concerning. We have a Kconfig for setting the IO_APIC ID: https://source.chromium. […] good catch; will write a patch -- To view, visit https://review.coreboot.org/c/coreboot/+/50513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Gerrit-Change-Number: 50513 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 21:44:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: add and use fch_enable_hpet_decode
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50512 ) Change subject: soc/amd: add and use fch_enable_hpet_decode ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/common/block/acpimmio/mmio_util.c: https://review.coreboot.org/c/coreboot/+/50512/comment/621bb7a6_ee6740e4 PS2, Line 79: HPET_FED0_EN > I feel like we should enable hpet_msi_en and hpet_width_sel. […] those are the default values after reset. might be a good idea to explicitly set/clear them to be sure that they're in the state we expect them to be in File src/soc/amd/common/block/include/amdblocks/acpimmio.h: https://review.coreboot.org/c/coreboot/+/50512/comment/6a622189_9b775dbd PS2, Line 20: FED0 > FED0? yes, there are two possible mappings for the hpet and the usual one that we'll be using and announcing in ACPI is at fed00000. or do you want me to add the remaining four zeros? -- To view, visit https://review.coreboot.org/c/coreboot/+/50512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Gerrit-Change-Number: 50512 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 21:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: 3rdparty/blobs: advance submodule pointer.
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50496 ) Change subject: 3rdparty/blobs: advance submodule pointer. ...................................................................... 3rdparty/blobs: advance submodule pointer. This adds the apcb binary for Bilby. Change-Id: I1487369bc72734e875c5a701f27ed2d6af41cd01 Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50496 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/3rdparty/blobs b/3rdparty/blobs index 353f246..02ab6c6 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 353f2469be53919b6b359148469485a9040e5a8b +Subproject commit 02ab6c66480ccd5f6bdfddd6fa090156d436fa4b -- To view, visit https://review.coreboot.org/c/coreboot/+/50496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1487369bc72734e875c5a701f27ed2d6af41cd01 Gerrit-Change-Number: 50496 Gerrit-PatchSet: 4 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
by Martin Roth (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Meera Ravindranath, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50241 ) Change subject: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Patchset: PS4: LGTM. I'd like others to weigh in as well though. File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/50241/comment/81f31d7c_f7fe8c64 PS4, Line 251: hope We shouldn't have to hope - This should be required of the UPD structure. -- To view, visit https://review.coreboot.org/c/coreboot/+/50241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d Gerrit-Change-Number: 50241 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 21:13:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add EC I/O decode windows
by Furquan Shaikh (Code Review) 11 Feb '21

11 Feb '21

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Change in coreboot[master]: mb/google/brya: Enable cr50 support
by Furquan Shaikh (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Tim Wawrzynczak, Boris Mittelberg. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50567 ) Change subject: mb/google/brya: Enable cr50 support ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/50567/comment/53bba2b2_f0e6e44d PS1, Line 5: : register "gpio_override_pm" = "1" : register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_2]" = "0" : register "gpio_pm[COMM_4]" = "0" : register "gpio_pm[COMM_5]" = "0" I think we are going to need the support like Volteer and Dedede to request cr50 to use long pulses. I think this is fine for now. Probably add a comment why this is done and raise a bug to follow-up on the required changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/50567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d Gerrit-Change-Number: 50567 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 21:08:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Add plain dsdt
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kyösti Mälkki, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50559 ) Change subject: mb/amd/majolica: Add plain dsdt ...................................................................... Patch Set 2: (1 comment) File src/mainboard/amd/majolica/dsdt.asl: https://review.coreboot.org/c/coreboot/+/50559/comment/bfafefc3_da3393a7 PS1, Line 3: #define MAINBOARD_HAS_SPEAKER 1 > The way this works, you don't need to define as 0. […] I can leave it off for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/50559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd71635d3493e0cf104b60ecf94ebdf70d512b94 Gerrit-Change-Number: 50559 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 20:55:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS
by Raul Rangel (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Paul Menzel. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50561 ) Change subject: include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50561/comment/99b88c79_9aa786ea PS2, Line 9: This is a magic value that means all processors. > Is it in some spec? Yeah, it's defined in the same section that describes the MADT: Local APIC NMI Structure. -- To view, visit https://review.coreboot.org/c/coreboot/+/50561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2fc060fda21bec44258bcae62ddb230be542759 Gerrit-Change-Number: 50561 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 11 Feb 2021 20:53:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add EC I/O decode windows
by Tim Wawrzynczak (Code Review) 11 Feb '21

11 Feb '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50568 ) Change subject: mb/google/brya: Add EC I/O decode windows ...................................................................... mb/google/brya: Add EC I/O decode windows BUG=b:180013349 TEST=console shows successful EC <-> SoC communications Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8 --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/50568/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 9ced455..79e0743 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,12 @@ device lapic 0 on end end + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gpio_override_pm" = "1" register "gpio_pm[COMM_0]" = "0" register "gpio_pm[COMM_1]" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/50568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8 Gerrit-Change-Number: 50568 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable cr50 support
by Tim Wawrzynczak (Code Review) 11 Feb '21

11 Feb '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50567 ) Change subject: mb/google/brya: Enable cr50 support ...................................................................... mb/google/brya: Enable cr50 support Add Kconfig options and devicetree entries for cr50 TPM. BUG=b:180017621 TEST=verify (via console) successful cr50 communications in verstage and payload (depthcharge). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/devicetree.cb 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/50567/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index ca76078..fbda4f7 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -13,6 +13,8 @@ select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 select SOC_INTEL_ALDERLAKE if BOARD_GOOGLE_BASEBOARD_BRYA @@ -30,6 +32,18 @@ string default "variants/baseboard/devicetree.cb" +config DRIVER_TPM_I2C_BUS + hex + default 0x3 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config TPM_TIS_ACPI_INTERRUPT + int + default 13 # GPE0_DW0_13 (GPP_A13_IRQ) + config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 647ea42..9ced455 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,13 @@ device lapic 0 on end end + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 @@ -90,6 +97,14 @@ device generic 0 on end end end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end device ref heci1 on end device ref sata on end device ref pcie_rp5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/50567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d Gerrit-Change-Number: 50567 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021