coreboot-gerrit December 2021

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Angel Pons, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59976/comment/593985b9_cab84174 PS10, Line 9: ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. : Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH. : If more than 4 PCH devices are connected on the platform, an external : differential buffer chip needs to be placed at the platform level. Please reflow for 75 characters per line. (Whole message.) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/59976/comment/e1fff69c_5902bd1d PS10, Line 41: int unsigned -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:25:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override EN_SPKR GPIO_70
by Kenneth Chan (Code Review) 09 Dec '21

09 Dec '21

Kenneth Chan has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59978 ) Change subject: mb/google/guybrush/var/dewatt: Override EN_SPKR GPIO_70 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/59978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf705e12f30ad145449be8d97cb214c56c02ec33 Gerrit-Change-Number: 59978 Gerrit-PatchSet: 4 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8186 Corsola review ToT
by Rex-BC Chen (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Rex-BC Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58639 to look at the new patch set (#45). Change subject: DO-NOT-SUBMIT: MT8186 Corsola review ToT ...................................................................... DO-NOT-SUBMIT: MT8186 Corsola review ToT Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 --- M README.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58639/45 -- To view, visit https://review.coreboot.org/c/coreboot/+/58639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 Gerrit-Change-Number: 58639 Gerrit-PatchSet: 45 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: setup open-drain ChromeOS pins
by Rex-BC Chen (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60002 to look at the new patch set (#2). Change subject: mb/google/corsola: setup open-drain ChromeOS pins ...................................................................... mb/google/corsola: setup open-drain ChromeOS pins Set GPIOs as input and high-z mode including: GPIO_SAR_INT_ODL/GPIO_BT_WAKE_AP_ODL/GPIO_WIFI_INT_ODL GPIO_DPBRDG_INT_ODL/GPIO_EDPBRDG_INT_ODL/GPIO_EC_AP_HPD_OD GPIO_TCHPAD_INT_ODL/GPIO_TCHSCR_INT_1V8_ODL/GPIO_EC_AP_INT_ODL GPIO_EC_IN_RW_ODL/GPIO_GSC_AP_INT_ODL/GPIO_AP_WP_ODL GPIO_HP_INT_ODL/GPIO_PEN_EJECT_OD/GPIO_UCAM_DET_ODL BUG=b:209342636 TEST=test pass on kingler board Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 --- M src/mainboard/google/corsola/bootblock.c M src/mainboard/google/corsola/chromeos.c M src/mainboard/google/corsola/gpio.h 3 files changed, 46 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/60002/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Gerrit-Change-Number: 60002 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Add Thermal Zone support
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Marshall Dawson. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52772 ) Change subject: mb/google/guybrush: Add Thermal Zone support ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52772/comment/4c5421bd_ddcd0368 PS1, Line 10: like line https://review.coreboot.org/c/coreboot/+/52772/comment/fb72927b_a95b7378 PS1, Line 9: The file thermal.asl is a : direct copy with the exception of removing an extra blank like and : declaring PPKG as External. Please fix Zork’s file first, and then copy it. File src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h: https://review.coreboot.org/c/coreboot/+/52772/comment/c12e942a_96c4dcb6 PS1, Line 6: /* : * Picasso Thermal Requirements : * TDP (W) 15 : * T die,max (°C) 105 : * T ctl,max 105 : * T die,lmt (default) 100 : * T ctl,lmt (default) 100 : */ If this is SoC specific, why not put it to the SoC directory? https://review.coreboot.org/c/coreboot/+/52772/comment/90ebd0ab_47f34365 PS1, Line 15: /* Control TDP Settings */ : #define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ : : /* Temperature which OS will shutdown at */ : #define CRITICAL_TEMPERATURE 104 : : /* Temperature which OS will throttle CPU */ : #define PASSIVE_TEMPERATURE 95 What is the source of these values? -- To view, visit https://review.coreboot.org/c/coreboot/+/52772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe0b7ed23f108e42abf7a9b13580b974fd61ec1 Gerrit-Change-Number: 52772 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:21:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: setup open-drain ChromeOS pins
by Rex-BC Chen (Code Review) 09 Dec '21

09 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60002 ) Change subject: mb/google/corsola: setup open-drain ChromeOS pins ...................................................................... mb/google/corsola: setup open-drain ChromeOS pins Set GPIOs as input and high-z mode including: GPIO_SAR_INT_ODL/GPIO_BT_WAKE_AP_ODL/GPIO_WIFI_INT_ODL GPIO_DPBRDG_INT_ODL/GPIO_EDPBRDG_INT_ODL/GPIO_EC_AP_HPD_OD GPIO_TCHPAD_INT_ODL/GPIO_TCHSCR_INT_1V8_ODL/GPIO_EC_AP_INT_ODL GPIO_EC_IN_RW_ODL/GPIO_GSC_AP_INT_ODL/GPIO_AP_WP_ODL GPIO_HP_INT_ODL/GPIO_PEN_EJECT_OD/GPIO_UCAM_DET_ODL BUG=b:209342636 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 --- M src/mainboard/google/corsola/bootblock.c M src/mainboard/google/corsola/chromeos.c M src/mainboard/google/corsola/gpio.h 3 files changed, 46 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/60002/1 diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index 0b03d04..71f1d36 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -12,5 +12,5 @@ mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_snfc_init(SPI_NOR_GPIO_SET1); setup_chromeos_gpios(); - gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING); + gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 847569e..ab54239 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -9,20 +9,35 @@ void setup_chromeos_gpios(void) { - gpio_input(GPIO_WP); - gpio_input_pullup(GPIO_EC_AP_INT); - gpio_input_pullup(GPIO_EC_IN_RW); - gpio_input_pullup(GPIO_GSC_AP_INT); - gpio_output(GPIO_EN_SPK, 0); + /* Setup open-drain pins */ + gpio_input(GPIO_SAR_INT_ODL); + gpio_input(GPIO_BT_WAKE_AP_ODL); + gpio_input(GPIO_WIFI_INT_ODL); + gpio_input(GPIO_DPBRDG_INT_ODL); + gpio_input(GPIO_EDPBRDG_INT_ODL); + gpio_input(GPIO_EC_AP_HPD_OD); + gpio_input(GPIO_TCHPAD_INT_ODL); + gpio_input(GPIO_TCHSCR_INT_1V8_ODL); + gpio_input(GPIO_EC_AP_INT_ODL); + gpio_input(GPIO_EC_IN_RW_ODL); + gpio_input(GPIO_GSC_AP_INT_ODL); + gpio_input(GPIO_AP_WP_ODL); + gpio_input(GPIO_HP_INT_ODL); + gpio_input(GPIO_PEN_EJECT_OD); + gpio_input(GPIO_UCAM_DET_ODL); + + /* Setup GPO */ gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_XHCI_DONE, 0); + gpio_output(GPIO_EN_SPK, 0); } void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, - {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, - {GPIO_GSC_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_EC_IN_RW_ODL.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"}, {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); @@ -31,10 +46,10 @@ int get_ec_is_trusted(void) { /* EC is trusted if not in RW. This is active low. */ - return !!gpio_get(GPIO_EC_IN_RW); + return !!gpio_get(GPIO_EC_IN_RW_ODL); } int tis_plat_irq_status(void) { - return gpio_eint_poll(GPIO_GSC_AP_INT); + return gpio_eint_poll(GPIO_GSC_AP_INT_ODL); } diff --git a/src/mainboard/google/corsola/gpio.h b/src/mainboard/google/corsola/gpio.h index 78dd252..f3bf5c9 100644 --- a/src/mainboard/google/corsola/gpio.h +++ b/src/mainboard/google/corsola/gpio.h @@ -5,14 +5,26 @@ #include <soc/gpio.h> -#define GPIO_EC_AP_INT GPIO(EINT13) -#define GPIO_WP GPIO(EINT16) -#define GPIO_BEEP_ON GPIO(PERIPHERAL_EN4) -#define GPIO_XHCI_DONE GPIO(PERIPHERAL_EN1) -#define GPIO_EC_IN_RW GPIO(EINT14) -#define GPIO_GSC_AP_INT GPIO(EINT15) -#define GPIO_EN_SPK GPIO(PERIPHERAL_EN3) -#define GPIO_RESET GPIO(PERIPHERAL_EN0) +#define GPIO_SAR_INT_ODL GPIO(EINT5) +#define GPIO_BT_WAKE_AP_ODL GPIO(EINT6) +#define GPIO_WIFI_INT_ODL GPIO(EINT7) +#define GPIO_DPBRDG_INT_ODL GPIO(EINT8) +#define GPIO_EDPBRDG_INT_ODL GPIO(EINT9) +#define GPIO_EC_AP_HPD_OD GPIO(EINT10) +#define GPIO_TCHPAD_INT_ODL GPIO(EINT11) +#define GPIO_TCHSCR_INT_1V8_ODL GPIO(EINT12) +#define GPIO_EC_AP_INT_ODL GPIO(EINT13) +#define GPIO_EC_IN_RW_ODL GPIO(EINT14) +#define GPIO_GSC_AP_INT_ODL GPIO(EINT15) +#define GPIO_AP_WP_ODL GPIO(EINT16) +#define GPIO_HP_INT_ODL GPIO(EINT17) +#define GPIO_PEN_EJECT_OD GPIO(EINT18) +#define GPIO_UCAM_DET_ODL GPIO(CAM_CLK2) + +#define GPIO_RESET GPIO(PERIPHERAL_EN0) +#define GPIO_XHCI_DONE GPIO(PERIPHERAL_EN1) +#define GPIO_EN_SPK GPIO(PERIPHERAL_EN3) +#define GPIO_BEEP_ON GPIO(PERIPHERAL_EN4) void setup_chromeos_gpios(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/60002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Gerrit-Change-Number: 60002 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{skylake/cannonlake}: Fix bug in vr_config
by Angel Pons (Code Review) 09 Dec '21

09 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60001 ) Change subject: soc/intel/{skylake/cannonlake}: Fix bug in vr_config ...................................................................... soc/intel/{skylake/cannonlake}: Fix bug in vr_config The `cpu_get_power_max()` function returns the TDP in milliwatts, but the vr_config code interprets the value in watts. Divide the value by 1000 to fix this. This also fixes an integer overflow when `cpu_get_power_max()` returns a value greater than 65535 (UINT16_MAX). Change-Id: Ibe9e0db6762eee5cc363f8b371c8538eb92f6308 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/vr_config.c M src/soc/intel/skylake/vr_config.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60001/1 diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 744564b..7ba73ea 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -619,7 +619,7 @@ FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params; const struct vr_config *cfg; static uint16_t mch_id = 0, igd_id = 0; - const uint16_t tdp = cpu_get_power_max(); + const uint16_t tdp = cpu_get_power_max() / 1000; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index d72fa1f..b807f54 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -62,7 +62,7 @@ static uint16_t get_sku_icc_max(int domain) { - const uint16_t tdp = cpu_get_power_max(); + const uint16_t tdp = cpu_get_power_max() / 1000; static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { -- To view, visit https://review.coreboot.org/c/coreboot/+/60001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9e0db6762eee5cc363f8b371c8538eb92f6308 Gerrit-Change-Number: 60001 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/var/ampton: add touchscreen into SSFC support
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Henry Sun, Paul2 Huang, Marco Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59859 ) Change subject: mb/google/octopus/var/ampton: add touchscreen into SSFC support ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59859/comment/b8b3110b_55dbc69b PS10, Line 9: Add ELAN9008 (eKTH6913UAY) support. Please add the datasheet name and revision. File src/mainboard/google/octopus/variants/ampton/variant.c: https://review.coreboot.org/c/coreboot/+/59859/comment/9367380c_69ffdde4 PS10, Line 39: if ((cfg != NULL && !strcmp(cfg->hid, "GTCH7502")) && : (touchscreen == SSFC_TOUCHSCREEN_DEFAULT)) { : printk(BIOS_INFO, "enable GTCH7502.\n"); : continue; : } Is this used on the device? -- To view, visit https://review.coreboot.org/c/coreboot/+/59859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0919d40a6c39ffaed52bb9e24a3509eb353127c Gerrit-Change-Number: 59859 Gerrit-PatchSet: 10 Gerrit-Owner: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:18:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake:[TEST] Enable PMC trace
by Sridhar Siricilla (Code Review) 09 Dec '21

09 Dec '21

Sridhar Siricilla has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/60000 ) Change subject: soc/intel/alderlake:[TEST] Enable PMC trace ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/60000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4d5189683202dd5e31ad21deb5c1cbc4581c478 Gerrit-Change-Number: 60000 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/alderlake:[TEST] Enable PMC trace
by Sridhar Siricilla (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Patrick Rudolph. Sridhar Siricilla has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/60000 ) Change subject: soc/intel/alderlake:[TEST] Enable PMC trace ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/60000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4d5189683202dd5e31ad21deb5c1cbc4581c478 Gerrit-Change-Number: 60000 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: deleteReviewer

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coreboot-gerrit December 2021