coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: brya: keep the same TPM I2C for 4ES variants
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: YH Lin, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59849 ) Change subject: brya: keep the same TPM I2C for 4ES variants ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59849/comment/77a2c62b_9e834255 PS4, Line 7: brya mb/google/brya -- To view, visit https://review.coreboot.org/c/coreboot/+/59849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Gerrit-Change-Number: 59849 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:47:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Add Elan touchscreen
by Kenneth Chan (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Paul Menzel, Ren Kuo, Rob Barnes, Karthikeyan Ramasubramanian, Karthik Ramasubramanian. Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59975 ) Change subject: mb/google/guybrush/var/dewatt: Add Elan touchscreen ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59975/comment/4520ef9f_c63ec27e PS2, Line 10: > Please add the datasheet name and revision. eKTH6918 product specification v0.5 , please refer to https://partnerissuetracker.corp.google.com/issues/208373433 #4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a7f5891e09ffa393c93881be68641d955efdf8 Gerrit-Change-Number: 59975 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:45:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/starlabs/labtop: Hook up Thunderbolt to CMOS
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Felix Singer, Sean Rhodes. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59705 ) Change subject: mainboard/starlabs/labtop: Hook up Thunderbolt to CMOS ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59705/comment/f5f5941f_00f541c5 PS5, Line 9: Hook up Thunderbolt and related settings to CMOS value : of `thunderbolt`. Changes TcssD3ColdDisable, TcssXhciEn, : and UsbTcPortEn. Please reflow for 72/75 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/59705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd Gerrit-Change-Number: 59705 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:44:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr: Correct displaying AMD fixed MTRRs
by Michał Żygowski (Code Review) 09 Dec '21

09 Dec '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60005 ) Change subject: cpu/x86/mtrr: Correct displaying AMD fixed MTRRs ...................................................................... cpu/x86/mtrr: Correct displaying AMD fixed MTRRs AMD Fixed MTRRs also contain DRAM read/write permissions which need to be accounted for when determining the memory type. Apply the correct mask on the MTRR type field when X86_AMD_FIXED_MTRRS are enabled. Also expose the rwdram bits in the fixed MTRRs so that the printed MTRR contents reflect the actual values stored in the registers. This allows better validation of AMD fixed MTRRs. TEST=Boot apu2 and display MTRRs. MTRR types reported are not reserved and the output displays rwdram bits correctly. Example: 0x0000000000000508: IA32_MTRRCAP: WC, FIX, 8 variable MTRRs 0x0000000000000c06: IA32_MTRR_DEF_TYPE: E, FE, WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX64K_00000 0x00000000 - 0x0007ffff: WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX16K_80000 0x00080000 - 0x0009ffff: WB 0x0000000000000000: IA32_MTRR_FIX16K_A0000 0x000a0000 - 0x000bffff: UC 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_C0000 0x000c0000 - 0x000c7fff: WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_C8000 0x000c8000 - 0x000cffff: WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_D0000 0x000d0000 - 0x000d7fff: WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_D8000 0x000d8000 - 0x000dffff: WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_E0000 0x000e0000 - 0x000e7fff: WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_E8000 0x000e8000 - 0x000effff: WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_F0000 0x000f0000 - 0x000f7fff: WB 0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_F8000 0x000f8000 - 0x000fffff: WB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Id9951f5e3702c04a4b06f6bf0de2f264d13292af --- M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/mtrr/debug.c M src/cpu/x86/mtrr/earlymtrr.c 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60005/1 diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 3f33e31..a78517a 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -3,6 +3,7 @@ romstage-y += earlymtrr.c bootblock-y += earlymtrr.c verstage_x86-y += earlymtrr.c +postcar-y += earlymtrr.c bootblock-y += debug.c romstage-y += debug.c diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c index 4ecae06..f8ae14c 100644 --- a/src/cpu/x86/mtrr/debug.c +++ b/src/cpu/x86/mtrr/debug.c @@ -28,12 +28,16 @@ uint32_t type; type = msr & MTRR_DEF_TYPE_MASK; + if (CONFIG(X86_AMD_FIXED_MTRRS)) + type &= 0x07; base_address = starting_address; next_address = base_address; for (index = 0; index < 64; index += 8) { next_address = starting_address + (memory_size * ((index >> 3) + 1)); next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; + if (CONFIG(X86_AMD_FIXED_MTRRS)) + next_type &= 0x07; if (next_type != type) { printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", base_address, next_address - 1, @@ -160,6 +164,8 @@ int i; int variable_mtrrs; + fixed_mtrrs_expose_amd_rwdram(); + /* Display the fixed MTRRs */ display_mtrrcap(); display_mtrr_def_type(); @@ -177,6 +183,8 @@ address_bits = cpu_phys_address_size(); address_mask = (1ULL << address_bits) - 1; + fixed_mtrrs_hide_amd_rwdram(); + /* Display the variable MTRRs */ variable_mtrrs = get_var_mtrr_count(); for (i = 0; i < variable_mtrrs; i++) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index aa301d0..b003291 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -1,11 +1,36 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/cpu.h> +#include <cpu/amd/mtrr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <console/console.h> #include <commonlib/bsd/helpers.h> +void fixed_mtrrs_expose_amd_rwdram(void) +{ + msr_t syscfg; + + if (!CONFIG(X86_AMD_FIXED_MTRRS)) + return; + + syscfg = rdmsr(SYSCFG_MSR); + syscfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg); +} + +void fixed_mtrrs_hide_amd_rwdram(void) +{ + msr_t syscfg; + + if (!CONFIG(X86_AMD_FIXED_MTRRS)) + return; + + syscfg = rdmsr(SYSCFG_MSR); + syscfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg); +} + /* Get first available variable MTRR. * Returns var# if available, else returns -1. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9951f5e3702c04a4b06f6bf0de2f264d13292af Gerrit-Change-Number: 60005 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: correct NOR flash configuration in GPIO set
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59945 ) Change subject: mb/google/corsola: correct NOR flash configuration in GPIO set ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Gerrit-Change-Number: 59945 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:43:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: setup open-drain ChromeOS pins
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60002 ) Change subject: mb/google/corsola: setup open-drain ChromeOS pins ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60002/comment/a60c3374_e77c3b0d PS2, Line 7: setup Set up https://review.coreboot.org/c/coreboot/+/60002/comment/f023379f_02b09088 PS2, Line 15: Please add the source for these settings. -- To view, visit https://review.coreboot.org/c/coreboot/+/60002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Gerrit-Change-Number: 60002 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:42:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: add tracker dump
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59990 ) Change subject: soc/mediatek/mt8186: add tracker dump ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59990/comment/d2e4511b_a7ef5a18 PS2, Line 14: TEST=build pass Please give an example, how to use it. -- To view, visit https://review.coreboot.org/c/coreboot/+/59990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2 Gerrit-Change-Number: 59990 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:42:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [DO NOT SUBMIT] Gerrit commit msg line length test
by Angel Pons (Code Review) 09 Dec '21

09 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60004 ) Change subject: [DO NOT SUBMIT] Gerrit commit msg line length test ...................................................................... [DO NOT SUBMIT] Gerrit commit msg line length test Looks like Gerrit wraps commit message lines at 72 characters, which can be useful when editing using the Gerrit web UI. This appears nicely with no soft wrapping being used. However, using 75 characters as line length limit for commit messages makes Gerrit soft-wrap the text on the web UI, which results in awful eyesores of commit messages in Gerrit's Web UI. While this is what the ancient coreboot wiki states, using 75 characters as line length limit doesn't go along well with Gerrit's current configuration. Change-Id: I1ce90f7be8e1f92cdb92e8aaafb4147dd19fe236 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A DONOTSUBMIT 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60004/1 diff --git a/DONOTSUBMIT b/DONOTSUBMIT new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/DONOTSUBMIT -- To view, visit https://review.coreboot.org/c/coreboot/+/60004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ce90f7be8e1f92cdb92e8aaafb4147dd19fe236 Gerrit-Change-Number: 60004 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: add support for tracker version one
by Paul Menzel (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Hung-Te Lin, Xi Chen, Rex-BC Chen, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59989 ) Change subject: soc/mediatek: add support for tracker version one ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59989/comment/2fc8e236_dbbd5dc9 PS1, Line 11: Please mention the datasheet names, versions and sections. File src/soc/mediatek/common/tracker.c: https://review.coreboot.org/c/coreboot/+/59989/comment/92ed6a0e_2832cd47 PS1, Line 9: __weak void tracker_setup(void) No weak function is needed, as it has to be implemented? -- To view, visit https://review.coreboot.org/c/coreboot/+/59989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Gerrit-Change-Number: 59989 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 11:41:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Paul Menzel, Angel Pons, Tim Wawrzynczak. Subrata Banik has uploaded a new patch set (#13) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... mb/intel/adlrvp: Add support for external clock buffer ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are connected on the platform, an external differential buffer chip needs to be placed at the platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/romstage_fsp_params.c 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59976/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021