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Subrata Banik has uploaded a new patch set (#12) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/59976 )
Change subject: mb/intel/adlrvp: Add support for external clock buffer
......................................................................
mb/intel/adlrvp: Add support for external clock buffer
ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7
SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4
PCH devices are connected on the platform, an external differential
buffer chip needs to be placed at the platform level.
A mainboard designer can choose to add an external clock chip, and select
the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER.
CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to
discrete buffer for further distribution to platform.
TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot.
localhost ~ # dmesg | grep mmc
[ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA
[ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa
[ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB
[ 5.494268] mmcblk0: p1
Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb
Signed-off-by: Subrata Banik <subi.banik(a)gmail.com>
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
2 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59976/12
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Change subject: mb/intel/adlrvp: Add support for external clock buffer
......................................................................
Patch Set 11:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59976/comment/8b0e7854_36a6e2bc
PS10, Line 9: ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals.
: Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH.
: If more than 4 PCH devices are connected on the platform, an external
: differential buffer chip needs to be placed at the platform level.
> Please reflow for 75 characters per line. (Whole message. […]
Ack
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/59976/comment/b9462ceb_ef6403b6
PS10, Line 41: int
> unsigned
Ack
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Change subject: soc/intel/{skylake/cannonlake}: Fix bug in vr_config
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Nice find.
Using units in a function names is a great way of avoiding such issues (in not strongly typed langue as C) ^^
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Change subject: mb/google/brya/var/taeko: Fix PLD group order(W/A)
......................................................................
Patch Set 5:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59973/comment/c179338f_24e429a4
PS5, Line 7: (W/A)
What does W/A emean?
https://review.coreboot.org/c/coreboot/+/59973/comment/7719707e_da109db2
PS5, Line 7: order(W/A)
Please add a space before (.
https://review.coreboot.org/c/coreboot/+/59973/comment/f388628a_8dcc2b57
PS5, Line 9: In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7)
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table) …
https://review.coreboot.org/c/coreboot/+/59973/comment/2f97a77a_aa599444
PS5, Line 9: In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue.
Please reflow for 75 characters per line.
https://review.coreboot.org/c/coreboot/+/59973/comment/2c7108c1_2e8b9f85
PS5, Line 9: table(667471b8d807da5a5a9277db47e069ad3b1351c7)
Please add a space before (.
https://review.coreboot.org/c/coreboot/+/59973/comment/f99ee9d0_4454b0ee
PS5, Line 10:
Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table")
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Change subject: mb/google/guybrush/var/dewatt: Add audio codec
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Was this change tested with ALC1019?
Only check 0x29 UU (i2cdetect, right side) and can't detect 0x2a UU for left side
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58772
to look at the new patch set (#11).
Change subject: amd/hda: Remove the weak function
......................................................................
amd/hda: Remove the weak function
BUG=b:140165023
Change-Id: I4b089b9fe4742b29686198f20fc7c1a2dae6f015
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/common/block/hda/Kconfig
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/northbridge.c
4 files changed, 10 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/58772/11
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Change subject: mb/google/guybrush/var/dewatt: Add Synaptics touchpad
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Was this change tested with S9831 touchpad?
Yes
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