coreboot-gerrit December 2021

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Change in coreboot[master]: vendorcode/intel: Add edk2-stable202111 support
by Angel Pons (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59986 ) Change subject: vendorcode/intel: Add edk2-stable202111 support ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4 Gerrit-Change-Number: 59986 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 09:46:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variant/taniks: Update devicetree settings
by Joey Peng (Code Review) 09 Dec '21

09 Dec '21

Joey Peng has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/59998 ) Change subject: mb/google/brya/variant/taniks: Update devicetree settings ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/59998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 Gerrit-Change-Number: 59998 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/brya/variant/taniks: Update devicetree settings
by Joey Peng (Code Review) 09 Dec '21

09 Dec '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59998 ) Change subject: mb/google/brya/variant/taniks: Update devicetree settings ...................................................................... mb/google/brya/variant/taniks: Update devicetree settings Based on schematic and gpio table of taniks, generate overridetree.cb settings for taniks. BUG=b:209926534 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: joey.peng(a)lcfc.corp-partner.google.com <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 --- M src/mainboard/google/brya/variants/taniks/Makefile.inc A src/mainboard/google/brya/variants/taniks/fw_config.c M src/mainboard/google/brya/variants/taniks/overridetree.cb 3 files changed, 516 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/59998/1 diff --git a/src/mainboard/google/brya/variants/taniks/Makefile.inc b/src/mainboard/google/brya/variants/taniks/Makefile.inc index db6b8eb..c61f75a 100644 --- a/src/mainboard/google/brya/variants/taniks/Makefile.inc +++ b/src/mainboard/google/brya/variants/taniks/Makefile.inc @@ -5,3 +5,5 @@ romstage-y += memory.c ramstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/taniks/fw_config.c b/src/mainboard/google/brya/variants/taniks/fw_config.c new file mode 100644 index 0000000..8a7c6b4 --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/fw_config.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */ + +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_NC(GPP_R7, NONE), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98357_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 4f2c04a..1b63230 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -1,6 +1,462 @@ +fw_config + field DB_USB 0 1 + option DB_USB_ABSENT 0 + option DB_USB3_WITH_A 1 + end + field DB_SD 2 3 + option DB_SD_ABSENT 0 + option DB_SD_OZ711LV2LN 1 + option DB_SD_GL9750 2 + option DB_SD_RTS5232S 3 + end + field KB_BL 4 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 5 7 + option AUDIO_UNKNOWN 0 + option AUDIO_MAX98357_ALC5682I_I2S 1 + end + field KB_LAYOUT 8 9 + option KB_LAYOUT_DEFAULT 0 + end + field WIFI_SAR_ID 10 11 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + option WIFI_SAR_ID_2 2 + option WIFI_SAR_ID_3 3 + end + field BOOT_NVME_MASK 12 + option BOOT_NVME_DISABLED 0 + option BOOT_NVME_ENABLED 1 + end + field BOOT_EMMC_MASK 13 + option BOOT_EMMC_DISABLED 0 + option BOOT_EMMC_ENABLED 1 + end +end chip soc/intel/alderlake + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + register "TcssAuxOri" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "SaGv" = "SaGv_Enabled" - device domain 0 on - end + register "PsysPmax" = "145" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" #DB Type-A Port A1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" # USB3/2 Type A port A1 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 74), + TEMP_PCT(75, 74), + TEMP_PCT(70, 74), + TEMP_PCT(65, 74), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 12000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 74, 4620, 115, 1150, }, + [4] = { 60, 4290, 90, 900, }, + [5] = { 45, 3980, 55, 550, }, + [6] = { 35, 3170, 30, 300, }, + [7] = { 30, 2640, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + }" + end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO AUDIO_MAX98357_ALC5682I_I2S + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + # Parameter T5 >= 180ms + register "generic.reset_delay_ms" = "180" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + # Parameter T1 >= 20ms + register "generic.enable_delay_ms" = "20" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "20" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO AUDIO_MAX98357_ALC5682I_I2S + end + end + end + device ref pcie_rp5 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp6 off end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on + probe DB_SD DB_SD_OZ711LV2LN + probe DB_SD DB_SD_GL9750 + probe DB_SD DB_SD_RTS5232S + end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + device generic 2 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(7, 1)" + device ref usb2_port7 on + probe DB_USB DB_USB3_WITH_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(9, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(9, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(7, 1)" + device ref usb3_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/59998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 Gerrit-Change-Number: 59998 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
by Bao Zheng (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 ) Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59918/comment/fde7c122_2958ba36 PS1, Line 8: > Where is that documented? Done File src/soc/amd/cezanne/chip.h: https://review.coreboot.org/c/coreboot/+/59918/comment/03999775_8267df11 PS1, Line 111: /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ > Does this mean you will apply the same tuning parameters to multiple DPs? Other DPs can be set in another request. -- To view, visit https://review.coreboot.org/c/coreboot/+/59918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Gerrit-Change-Number: 59918 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 09 Dec 2021 09:24:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Google/Nipperkin: Add board specific values for eDP tuning
by Bao Zheng (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Paul Menzel, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59919 to look at the new patch set (#5). Change subject: Google/Nipperkin: Add board specific values for eDP tuning ...................................................................... Google/Nipperkin: Add board specific values for eDP tuning These values are got from experiment. The document can be got from the issue tracker of this ticket. BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59919/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Gerrit-Change-Number: 59919 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
by Bao Zheng (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59918 to look at the new patch set (#4). Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning ...................................................................... soc/amd/cezanne: FSP: Add UPD entry for eDP tuning The document about eDP tuning is attached in issue tracker of this ticket. BUG=b:203061533 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 3 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59918/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Gerrit-Change-Number: 59918 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Google/Nipperkin: Add board specific values for eDP tuning
by Bao Zheng (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Paul Menzel, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59919 ) Change subject: Google/Nipperkin: Add board specific values for eDP tuning ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59919/comment/24c03be5_c79f1852 PS1, Line 8: > Please document, where you got the values from. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Gerrit-Change-Number: 59919 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 09 Dec 2021 09:18:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Google/Nipperkin: Add board specific values for eDP tuning
by Bao Zheng (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Paul Menzel, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59919 to look at the new patch set (#4). Change subject: Google/Nipperkin: Add board specific values for eDP tuning ...................................................................... Google/Nipperkin: Add board specific values for eDP tuning These values are got from experiment. The document can be got from the issue tracker of this ticket. BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59919/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Gerrit-Change-Number: 59919 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Google/Nipperkin: Add board specific values for eDP tuning
by Bao Zheng (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Paul Menzel, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59919 to look at the new patch set (#3). Change subject: Google/Nipperkin: Add board specific values for eDP tuning ...................................................................... Google/Nipperkin: Add board specific values for eDP tuning These values are got from experiment. The document can be got from the issue tracker of this ticker. BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59919/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Gerrit-Change-Number: 59919 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/octopus: add ALC5682I-VS to be supported in the SSFC
by Marco Chen (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Henry Sun, Paul Menzel, Paul2 Huang. Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59856 ) Change subject: mb/google/octopus: add ALC5682I-VS to be supported in the SSFC ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/octopus/mainboard.c: https://review.coreboot.org/c/coreboot/+/59856/comment/760abdee_5970a453 PS4, Line 218: cfg->hid = "RTL5682"; > Just a guess - the `register "name" = ""RT58""` is the same between VD and VS objects so maybe we do […] More discussion in b/209707713 and the result is that objects in a single slave address will be seen as one only. Therefore we can only have 1 object and update HID accordingly based on SSFC config as early patch designed. -- To view, visit https://review.coreboot.org/c/coreboot/+/59856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8 Gerrit-Change-Number: 59856 Gerrit-PatchSet: 6 Gerrit-Owner: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 08:27:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021