coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/brya/var/taeko: Fix PLD group order(WR)
by Tim Wawrzynczak (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Kevin Chang, YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59973 ) Change subject: mb/google/brya/var/taeko: Fix PLD group order(WR) ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59973/comment/5bf8daa0_69ff6371 PS2, Line 7: (WR) > It is mean workaround or I need make it to WA? Ahh ok, I am more familiar with `W/A` -- To view, visit https://review.coreboot.org/c/coreboot/+/59973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4cf2d735de524ae721800600536923d1d47f04b Gerrit-Change-Number: 59973 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Thu, 09 Dec 2021 02:05:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Fix PLD group order(WR)
by Kevin Chang (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Tim Wawrzynczak, YH Lin. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59973 ) Change subject: mb/google/brya/var/taeko: Fix PLD group order(WR) ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59973/comment/1919553b_71bad9d5 PS2, Line 7: (WR) > sorry, I don't understand what `(WR)` means ? It is mean workaround or I need make it to WA? https://review.coreboot.org/c/coreboot/+/59973/comment/8a66d962_14134b70 PS2, Line 9: In ec/google/chromeec: Add PLD to EC conn in ACPI : table(667471b8d807da5a5a9277db47e069ad3b1351c7), : PLD is added to ACPI table. It causes the DUT to : not boot into the OS. So fix the USB3/USB2 Type-C : Port C2 PLD group order from 3 to 2 to solve this : issue. > commit messages are 72 characters wide Updated in latest patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/59973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4cf2d735de524ae721800600536923d1d47f04b Gerrit-Change-Number: 59973 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Thu, 09 Dec 2021 02:04:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: correct NOR flash configuration in GPIO set
by Rex-BC Chen (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59945 ) Change subject: mb/google/corsola: correct NOR flash configuration in GPIO set ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59945/comment/f845268e_5a829b96 PS7, Line 7: kingler/krabby : : Kingler and krabby boards use GPIO_SET1 for NOR flash. > I'd agree it will be confusing when you list the board names here but no configs in the implementati […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Gerrit-Change-Number: 59945 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 09 Dec 2021 02:03:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: add tracker dump
by Rex-BC Chen (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59990 ) Change subject: soc/mediatek/mt8186: add tracker dump ...................................................................... soc/mediatek/mt8186: add tracker dump Tracker is a debugging tool, and MT8186 only supports AP tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2 --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/bootblock.c M src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/tracker.h 4 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59990/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 7a2f997..2a22e6e 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -11,6 +11,7 @@ bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c +bootblock-y += ../common/tracker.c ../common/tracker_v1.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c wdt.c diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c index d5b288a..e5d1e73 100644 --- a/src/soc/mediatek/mt8186/bootblock.c +++ b/src/soc/mediatek/mt8186/bootblock.c @@ -5,11 +5,13 @@ #include <soc/gic.h> #include <soc/mmu_operations.h> #include <soc/pll.h> +#include <soc/tracker_common.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + bustracker_init(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index 6a5ce5c..adb1d59 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -42,6 +42,7 @@ I2C8_DMA_BASE = IO_PHYS + 0x00200A80, I2C9_DMA_BASE = IO_PHYS + 0x00200C00, DEVAPC_BASE = IO_PHYS + 0x00207000, + DBG_TRACKER_BASE = IO_PHYS + 0x00208000, EMI0_BASE = IO_PHYS + 0x00219000, EMI0_MPU_BASE = IO_PHYS + 0x0021B000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00220000, diff --git a/src/soc/mediatek/mt8186/include/soc/tracker.h b/src/soc/mediatek/mt8186/include/soc/tracker.h new file mode 100644 index 0000000..0f838b6 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/tracker.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.13 + */ + +#ifndef SOC_MEDIATEK_MT8186_TRACKER_H +#define SOC_MEDIATEK_MT8186_TRACKER_H + +#include <soc/tracker_v1.h> + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2 Gerrit-Change-Number: 59990 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: add support for tracker version one
by Rex-BC Chen (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59989 ) Change subject: soc/mediatek: add support for tracker version one ...................................................................... soc/mediatek: add support for tracker version one There are two versions for tracker system: Version 1 for MT8186, and version 2 for MT8192 and MT8195. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 --- M src/soc/mediatek/common/include/soc/tracker_common.h A src/soc/mediatek/common/include/soc/tracker_v1.h A src/soc/mediatek/common/include/soc/tracker_v2.h M src/soc/mediatek/common/tracker.c A src/soc/mediatek/common/tracker_v1.c A src/soc/mediatek/common/tracker_v2.c M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/tracker.h M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/tracker.h 10 files changed, 184 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59989/1 diff --git a/src/soc/mediatek/common/include/soc/tracker_common.h b/src/soc/mediatek/common/include/soc/tracker_common.h index a68d329..0269457 100644 --- a/src/soc/mediatek/common/include/soc/tracker_common.h +++ b/src/soc/mediatek/common/include/soc/tracker_common.h @@ -1,25 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_TRACKER_H -#define SOC_MEDIATEK_COMMON_TRACKER_H +#ifndef SOC_MEDIATEK_TRACKER_COMMON_H +#define SOC_MEDIATEK_TRACKER_COMMON_H -#define BUS_DBG_CON 0x000 -#define BUS_DBG_TIMER_CON0 0x004 -#define BUS_DBG_TIMER_CON1 0x008 -#define BUS_TRACE_CON_1 0x900 -#define BUS_TRACE_CON_AO_1 0x9FC -#define BUS_TRACE_CON_2 0xA00 -#define BUS_TRACE_CON_AO_2 0xAFC -#define BUS_TRACE_EN 16 - -#define SYS_TRACK_ENTRY 64 -#define INFRA_ENTRY_NUM 32 -#define PERI_ENTRY_NUM 16 - -#define AR_TRACK_OFFSET 0x0100 -#define AW_TRACK_OFFSET 0x0300 - -#define BUSTRACKER_TIMEOUT 0x300 +#include <stdint.h> #define BUS_DBG_CON_IRQ_AR_STA0 0x00000100 #define BUS_DBG_CON_IRQ_AW_STA0 0x00000200 @@ -28,13 +12,17 @@ #define BUS_DBG_CON_TIMEOUT (BUS_DBG_CON_IRQ_AR_STA0 | BUS_DBG_CON_IRQ_AW_STA0 | \ BUS_DBG_CON_IRQ_AR_STA1 | BUS_DBG_CON_IRQ_AW_STA1) -enum { - TRACKER_SYSTRACKER = 0, - TRACKER_INFRATRACKER, - TRACKER_PERISYSTRACKER, - TRACKER_NUM, +struct tracker { + uintptr_t base_addr; + u32 timeout; + u32 entry; + u32 offset[2]; + const char *str; }; +extern struct tracker tracker_data[]; + +void tracker_setup(void); void bustracker_init(void); #endif diff --git a/src/soc/mediatek/common/include/soc/tracker_v1.h b/src/soc/mediatek/common/include/soc/tracker_v1.h new file mode 100644 index 0000000..e2a4b67 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/tracker_v1.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_TRACKER_V1_H +#define SOC_MEDIATEK_TRACKER_V1_H + +#define SYS_TRACK_ENTRY 8 + +#define AR_TRACK_OFFSET 0x0100 +#define AW_TRACK_OFFSET 0x0200 + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_NUM, +}; + +#endif diff --git a/src/soc/mediatek/common/include/soc/tracker_v2.h b/src/soc/mediatek/common/include/soc/tracker_v2.h new file mode 100644 index 0000000..e7bf8df --- /dev/null +++ b/src/soc/mediatek/common/include/soc/tracker_v2.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_TRACKER_V2_H +#define SOC_MEDIATEK_TRACKER_V2_H + +#define BUS_DBG_CON 0x000 +#define BUS_DBG_TIMER_CON0 0x004 +#define BUS_DBG_TIMER_CON1 0x008 +#define BUS_TRACE_CON_1 0x900 +#define BUS_TRACE_CON_AO_1 0x9FC +#define BUS_TRACE_CON_2 0xA00 +#define BUS_TRACE_CON_AO_2 0xAFC +#define BUS_TRACE_EN 16 + +#define SYS_TRACK_ENTRY 64 +#define INFRA_ENTRY_NUM 32 +#define PERI_ENTRY_NUM 16 + +#define AR_TRACK_OFFSET 0x0100 +#define AW_TRACK_OFFSET 0x0300 + +#define BUSTRACKER_TIMEOUT 0x300 + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_INFRATRACKER, + TRACKER_PERISYSTRACKER, + TRACKER_NUM, +}; + +#endif diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 6d4e6b2..3485449 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -1,79 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdio.h> #include <console/console.h> #include <device/mmio.h> #include <soc/addressmap.h> +#include <soc/tracker.h> #include <soc/tracker_common.h> -static struct tracker { - uintptr_t base_addr; - u32 timeout; - u32 entry; - u32 offset[2]; - const char *str; -} tracker_data[TRACKER_NUM] = { - [TRACKER_SYSTRACKER] = { - .base_addr = DBG_TRACKER_BASE, - .timeout = BUS_DBG_CON_TIMEOUT, - .entry = SYS_TRACK_ENTRY, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "systracker", - }, - [TRACKER_INFRATRACKER] = { - .base_addr = INFRA_TRACKER_BASE, - .timeout = BUSTRACKER_TIMEOUT, - .entry = INFRA_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "infra_tracker", - }, - [TRACKER_PERISYSTRACKER] = { - .base_addr = PERI_TRACKER_BASE, - .timeout = BUSTRACKER_TIMEOUT, - .entry = PERI_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "peri_tracker", - }, -}; - -static void setup_init(void) +__weak void tracker_setup(void) { - u32 val; - /* - * Set infra/peri tracker timeout. - * timeout = clock_in_mhz * 1000 / 16 * timeout_in_ms - * - * timeout: 200ms - * infra tracker clock: 156MHz - * peri tracker clock: 78MHz - */ - val = 156 * 1000 / 16 * 200; - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); - - val = 78 * 1000 / 16 * 200; - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); - - /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); - - /* - * Enable infra/peri tracker. - * bit[0] - BUS_DBG_EN - * bit[1] - TIMEOUT_EN - * bit[2] - SLV_ERR_EN - * bit[13] - HALT_ON_TIMEOUT_EN - * bit[14] - BUS_OT_WEN_CTRL - */ - val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); - + /* do nothing. */ } static void tracker_dump_data(void) @@ -91,19 +26,6 @@ printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); for (k = 0; k < 2; k++) { - /* - * for systracker: - * offset[0] dump from offset 0x100 ~ 0x2F8. - * offset[1] dump from offset 0x300 ~ 0x4FC - * - * for infra tracker: - * offset[0] dump from offset 0x100 ~ 0x1F8 - * offset[1] dump from offset 0x300 ~ 0x3FC - * - * for perisys tracker: - * offset[0] dump from offset 0x100 ~ 0x2F8 - * offset[1] dump from offset 0x300 ~ 0x4FC - */ size = 2 * tra->entry; for (i = 0; i < size; i++) { reg = tra->base_addr + tra->offset[k] + i * 4; @@ -121,5 +43,5 @@ void bustracker_init(void) { tracker_dump_data(); - setup_init(); + tracker_setup(); } diff --git a/src/soc/mediatek/common/tracker_v1.c b/src/soc/mediatek/common/tracker_v1.c new file mode 100644 index 0000000..746951b --- /dev/null +++ b/src/soc/mediatek/common/tracker_v1.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/addressmap.h> +#include <soc/tracker.h> +#include <soc/tracker_common.h> + +/* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x13C. + * offset[1] dump from offset 0x200 ~ 0x23C. + */ +struct tracker tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = DBG_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "systracker", + }, +}; diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c new file mode 100644 index 0000000..fecde16 --- /dev/null +++ b/src/soc/mediatek/common/tracker_v2.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/tracker.h> +#include <soc/tracker_common.h> + +/* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x2F8. + * offset[1] dump from offset 0x300 ~ 0x4FC + * + * for infra tracker: + * offset[0] dump from offset 0x100 ~ 0x1F8 + * offset[1] dump from offset 0x300 ~ 0x3FC + * + * for perisys tracker: + * offset[0] dump from offset 0x100 ~ 0x2F8 + * offset[1] dump from offset 0x300 ~ 0x4FC + */ +struct tracker tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = DBG_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "systracker", + }, + [TRACKER_INFRATRACKER] = { + .base_addr = INFRA_TRACKER_BASE, + .timeout = BUSTRACKER_TIMEOUT, + .entry = INFRA_ENTRY_NUM, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "infra_tracker", + }, + [TRACKER_PERISYSTRACKER] = { + .base_addr = PERI_TRACKER_BASE, + .timeout = BUSTRACKER_TIMEOUT, + .entry = PERI_ENTRY_NUM, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "peri_tracker", + }, +}; + +void tracker_setup(void) +{ + u32 val; + /* + * Set infra/peri tracker timeout. + * timeout = clock_in_mhz * 1000 / 16 * timeout_in_ms + * + * timeout: 200ms + * infra tracker clock: 156MHz + * peri tracker clock: 78MHz + */ + val = 156 * 1000 / 16 * 200; + write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + + val = 78 * 1000 / 16 * 200; + write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + + /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + + /* + * Enable infra/peri tracker. + * bit[0] - BUS_DBG_EN + * bit[1] - TIMEOUT_EN + * bit[2] - SLV_ERR_EN + * bit[13] - HALT_ON_TIMEOUT_EN + * bit[14] - BUS_OT_WEN_CTRL + */ + val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); +} diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index b04acb5..aeb50a7 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,7 +10,7 @@ bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c -bootblock-y += ../common/tracker.c +bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c diff --git a/src/soc/mediatek/mt8192/include/soc/tracker.h b/src/soc/mediatek/mt8192/include/soc/tracker.h new file mode 100644 index 0000000..0b62811 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/tracker.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_TRACKER_H +#define SOC_MEDIATEK_MT8192_TRACKER_H + +#include <soc/tracker_v2.h> + +#endif diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index a7ada28..8ab78a8 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -7,7 +7,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c -bootblock-y += ../common/tracker.c +bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8195/include/soc/tracker.h b/src/soc/mediatek/mt8195/include/soc/tracker.h new file mode 100644 index 0000000..293ce3c --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/tracker.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_TRACKER_H +#define SOC_MEDIATEK_MT8195_TRACKER_H + +#include <soc/tracker_v2.h> + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Gerrit-Change-Number: 59989 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: correct NOR flash configuration in GPIO set
by Rex-BC Chen (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Rex-BC Chen, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59945 to look at the new patch set (#8). Change subject: mb/google/corsola: correct NOR flash configuration in GPIO set ...................................................................... mb/google/corsola: correct NOR flash configuration in GPIO set The reference design has changed to use GPIO SET1 for NOR flash. There are no devices already built using SET0 so we can safely change the implementation without conditional configs. Reference document: kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11. crab_proto 0_2021112.pdf, page 11. BUG=b:202871018 TEST=flash verify pass on kingler on bootblock stage Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f --- M src/mainboard/google/corsola/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/59945/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Gerrit-Change-Number: 59945 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: revise GPIO set of NOR flash for kingler/krabby
by Hung-Te Lin (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Rex-BC Chen, Paul Menzel. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59945 ) Change subject: mb/google/corsola: revise GPIO set of NOR flash for kingler/krabby ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59945/comment/40e98955_ea4898ab PS7, Line 7: kingler/krabby : : Kingler and krabby boards use GPIO_SET1 for NOR flash. I'd agree it will be confusing when you list the board names here but no configs in the implementation checking boards. Let's try this: mb/google/corsola: correct NOR flash configuration in GPIO set The reference design has changed to use GPIO SET1 for NOR flash. There are no devices already built using SET0 so we can safely change the implementation without conditional configs. -- To view, visit https://review.coreboot.org/c/coreboot/+/59945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Gerrit-Change-Number: 59945 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 09 Dec 2021 01:56:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: get SKU ID
by Hung-Te Lin (Code Review) 09 Dec '21

09 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59944 ) Change subject: mb/google/corsola: get SKU ID ...................................................................... mb/google/corsola: get SKU ID Retrieve the SKU ID for Corsola via CBI interface. If that failed (or no data found), fallback to ADC channels for SKU ID. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59944 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/boardid.c 2 files changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 8877f2f..193cafd 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -23,6 +23,7 @@ select COMMONLIB_STORAGE_MMC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c index 285b065..96031ef 100644 --- a/src/mainboard/google/corsola/boardid.c +++ b/src/mainboard/google/corsola/boardid.c @@ -3,6 +3,7 @@ #include <assert.h> #include <boardid.h> #include <console/console.h> +#include <ec/google/chromeec/ec.h> #include <soc/auxadc.h> /* board_id is provided by ec/google/chromeec/ec_boardid.c */ @@ -13,6 +14,9 @@ /* RAM IDs */ RAM_ID_LOW_CHANNEL = 2, RAM_ID_HIGH_CHANNEL = 3, + /* SKU IDs */ + SKU_ID_LOW_CHANNEL = 4, + SKU_ID_HIGH_CHANNEL = 5, }; static const unsigned int ram_voltages[ADC_LEVELS] = { @@ -34,6 +38,8 @@ static const unsigned int *adc_voltages[] = { [RAM_ID_LOW_CHANNEL] = ram_voltages, [RAM_ID_HIGH_CHANNEL] = ram_voltages, + [SKU_ID_LOW_CHANNEL] = ram_voltages, + [SKU_ID_HIGH_CHANNEL] = ram_voltages, }; static uint32_t get_adc_index(unsigned int channel) @@ -54,6 +60,24 @@ return id; } +uint32_t sku_id(void) +{ + static uint32_t cached_sku_code = BOARD_ID_INIT; + + if (cached_sku_code == BOARD_ID_INIT) { + cached_sku_code = google_chromeec_get_board_sku(); + + if (cached_sku_code == CROS_SKU_UNKNOWN) { + printk(BIOS_WARNING, "Failed to get SKU code from EC\n"); + cached_sku_code = (get_adc_index(SKU_ID_HIGH_CHANNEL) << 4 | + get_adc_index(SKU_ID_LOW_CHANNEL)); + } + printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code); + } + + return cached_sku_code; +} + uint32_t ram_code(void) { static uint32_t cached_ram_code = BOARD_ID_INIT; -- To view, visit https://review.coreboot.org/c/coreboot/+/59944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Gerrit-Change-Number: 59944 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by Hung-Te Lin (Code Review) 09 Dec '21

09 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59955 ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 586aafa3a: 2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration) to commit id 73193689c: 2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration) This brings in 684 new commits. Change-Id: I4173f3cb646839ad12c4e43e8c50b0be53364f04 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59955 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M 3rdparty/arm-trusted-firmware 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 586aafa..7319368 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 586aafa3a4b13971339f78e430075592c3fe74b5 +Subproject commit 73193689c0e9cf13ad0ddbb9da25e9a66c4e14b3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4173f3cb646839ad12c4e43e8c50b0be53364f04 Gerrit-Change-Number: 59955 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brask: Configure the ISOLATE pin of LAN
by Hou-hsun Lee (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, Alan Huang. Hou-hsun Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58105 ) Change subject: mb/google/brya/var/brask: Configure the ISOLATE pin of LAN ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/brya/variants/brask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/58105/comment/eab9c424_dc4d7516 PS5, Line 86: register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)" > Thanks for clarification. I don't have concern for this now. […] GPP_A7 should be the LAN_WAKE_ODL pin according to https://partnerissuetracker.corp.google.com/issues/204289108#comment23. GPP_H22 is the ISOLATE pin for RT8125, which relates to the s0ix function. Is this patch ready to be merged? -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 9 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 09 Dec 2021 01:40:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021