coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5525 discussions

Change in coreboot[master]: payloads/Makefile.inc: Add warning for image built with no payload
by Nicholas Chin (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Nico Huber, Raul Rangel, Tim Wawrzynczak, Angel Pons. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60025 ) Change subject: payloads/Makefile.inc: Add warning for image built with no payload ...................................................................... Patch Set 3: (1 comment) File payloads/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60025/comment/320bb94d_b729d8b7 PS1, Line 60: printf "You can use cbfstool to add a payload to the image.\n\n" > Nit, the text block looks very unbalanced. Moving "board's" to the next […] Tweaked lines and rebased onto master -- To view, visit https://review.coreboot.org/c/coreboot/+/60025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 Gerrit-Change-Number: 60025 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: AreYouLoco? <areyouloco(a)paranoici.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 19 Dec 2021 16:38:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/Makefile.inc: Add warning for image built with no payload
by Nicholas Chin (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Angel Pons, Nicholas Chin. Hello AreYouLoco?, build bot (Jenkins), Nico Huber, Raul Rangel, Tim Wawrzynczak, Paul Menzel, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60025 to look at the new patch set (#3). Change subject: payloads/Makefile.inc: Add warning for image built with no payload ...................................................................... payloads/Makefile.inc: Add warning for image built with no payload Writing a coreboot image without a payload to a board's flash chip will result in a non-bootable system, so warn the user if this is the case. Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 --- M payloads/Makefile.inc 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/60025/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 Gerrit-Change-Number: 60025 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: AreYouLoco? <areyouloco(a)paranoici.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya: Allow variants to choose CAR setup configuration
by Subrata Banik (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59272 ) Change subject: mb/google/brya: Allow variants to choose CAR setup configuration ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/59272/comment/fd93956d_2b134e68 PS3, Line 134: BOARD_GOOGLE_BRYA0 > @Tim, Ping! @Tim/Nick: any update on retiring the old Brya boards so we can enable eNEM support by default or if you would like to enable eNEM for OEM boards as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/59272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe94e6b82739ec65829859271622d904d75e978d Gerrit-Change-Number: 59272 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 19 Dec 2021 13:21:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [TESTME] nb/intel/ironlake: Fix some quickpath init magic
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Paul Menzel, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60216 ) Change subject: [TESTME] nb/intel/ironlake: Fix some quickpath init magic ...................................................................... Patch Set 2: (1 comment) File src/northbridge/intel/ironlake/raminit.c: https://review.coreboot.org/c/coreboot/+/60216/comment/741656aa_091c8f82 PS1, Line 3396: rdmsr(0x1ac); // !!!! > Hmmm, apparently this MSR is also read here for something else. Left this rdmsr() call as-is for now because it's not related to this change. Reading this MSR has no side-effects. -- To view, visit https://review.coreboot.org/c/coreboot/+/60216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Gerrit-Change-Number: 60216 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 19 Dec 2021 12:58:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard/starlabs: Add LabTop Mk IV
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mainboard/starlabs: Add LabTop Mk IV ...................................................................... Patch Set 68: Code-Review+1 (2 comments) File Documentation/mainboard/starlabs/labtop_cml.md: https://review.coreboot.org/c/coreboot/+/58428/comment/0099a9e4_f184b80c PS66, Line 40: [^1] What does this mean? File src/mainboard/starlabs/labtop/dsdt.asl: https://review.coreboot.org/c/coreboot/+/58428/comment/a1d61c23_b2022408 PS66, Line 3: #if CONFIG(BOARD_STARLABS_STARBOOK_TGL) : #define EC_GPE_SCI 0x6e : #else : #define EC_GPE_SCI 0x50 : #endif Idea for another patch: Turn this into a Kconfig option -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 68 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Sun, 19 Dec 2021 12:56:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [TESTME] nb/intel/ironlake: Make raminit more magic
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60223 ) Change subject: [TESTME] nb/intel/ironlake: Make raminit more magic ...................................................................... [TESTME] nb/intel/ironlake: Make raminit more magic Change-Id: I7e09cc67ab64699121ba75fb5473b93194d8f36f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/ironlake/raminit.h 2 files changed, 134 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/60223/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index da506ac..6162085 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -241,11 +241,12 @@ } } -static void write_26c(int channel, u16 si) +static void write_26c(int channel, u16 clock_speed) { + const u16 reftimeout = clock_speed * 7800 / 900; mchbar_write32(0x26c + (channel << 10), 0x03243f35); - mchbar_write32(0x268 + (channel << 10), 0xcfc00000 | si << 9); - mchbar_write16(0x2b9 + (channel << 10), si); + mchbar_write32(0x268 + (channel << 10), 0xcfc00000 | reftimeout << 9); + mchbar_write16(0x2b9 + (channel << 10), reftimeout); } static void toggle_1d0_142_5ff(void) @@ -765,10 +766,12 @@ 375; some_delay_3_ps = halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info); + info->some_delay_3_halfcycles = 0; if (info->revision_flag_1) { if (some_delay_3_ps >= 150) { const int some_delay_3_halfcycles = (some_delay_3_ps << 6) / halfcycle_ps(info); + info->some_delay_3_halfcycles = some_delay_3_halfcycles; some_delay_3_ps_rounded = halfcycle_ps(info) * some_delay_3_halfcycles >> 6; } @@ -784,6 +787,7 @@ some_delay_2_halfcycles_ceil - 1; if (!info->revision_flag_1) some_delay_2_halfcycles_floor++; + info->some_delay_2_halfcycles_floor = some_delay_2_halfcycles_floor; info->some_delay_2_halfcycles_ceil = some_delay_2_halfcycles_ceil; info->some_delay_3_ps_rounded = some_delay_3_ps_rounded; if ((info->populated_ranks[0][0][0] && info->populated_ranks[0][1][0]) @@ -910,6 +914,11 @@ info->avg4044[channel] = sum / count; info->max4048[channel] = max_of_unk; } + if (info->silicon_revision == 2 || info->silicon_revision == 3) + info->revision_flag_2 = 0; + else + info->revision_flag_2 = 1; + } static void jedec_read(struct raminfo *info, @@ -1229,7 +1238,7 @@ cas_latency_derived << 16 | 0x4700000); mchbar_write32(0x258 + (channel << 10), (info->board_lane_delay[5] + info->clock_speed_index + 9) << 12 | - (info->clock_speed_index - info->cas_latency + 12) << 8 | + (info->clock_speed_index + 12 - info->cas_latency) << 8 | info->board_lane_delay[2] << 17 | info->board_lane_delay[4] << 24 | 0x47); mchbar_write32(0x25c + (channel << 10), @@ -3156,7 +3165,7 @@ info.last_500_command[0] = 0; info.last_500_command[1] = 0; - +/* info.board_lane_delay[0] = 0x14; info.board_lane_delay[1] = 0x07; info.board_lane_delay[2] = 0x07; @@ -3166,6 +3175,16 @@ info.board_lane_delay[6] = 0x04; info.board_lane_delay[7] = 0x05; info.board_lane_delay[8] = 0x10; +*/ + info.board_lane_delay[0] = 0x18; + info.board_lane_delay[1] = 0x07; + info.board_lane_delay[2] = 0x07; + info.board_lane_delay[3] = 0x08; + info.board_lane_delay[4] = 0x4a; + info.board_lane_delay[5] = 0x04; + info.board_lane_delay[6] = 0x04; + info.board_lane_delay[7] = 0x05; + info.board_lane_delay[8] = 0x10; info.training.reg_178 = 0; info.training.reg_10b = 0; @@ -3362,25 +3381,88 @@ write_1d0(0, 0x33d, 0, 0); write_500(&info, 0, 0, 0xb61, 0, 0); write_500(&info, 1, 0, 0xb61, 0, 0); - mchbar_write32(0x1a30, 0); + mchbar_write32(0x1a30, (info.revision < 0x8) << 18); mchbar_write32(0x1a34, 0); + mchbar_write16(0x614, 0xb5b | (info.populated_ranks[1][0][0] * 0x404) | (info.populated_ranks[0][0][0] * 0xa0)); mchbar_write16(0x616, 0x26a); mchbar_write32(0x134, 0x856000); mchbar_write32(0x160, 0x5ffffff); - mchbar_clrsetbits32(0x114, ~0, 0xc2024440); // !!!! - mchbar_clrsetbits32(0x118, ~0, 0x4); // !!!! - for (channel = 0; channel < NUM_CHANNELS; channel++) - mchbar_write32(0x260 + (channel << 10), 0x30809ff | - (info.populated_ranks_mask[channel] & 3) << 20); + { + u8 val8 = 0; + u32 val32 = 0x2024400; + if (info.revision_flag_2 == 1) { + if (info.clock_speed_index > 2) + val8 = 1; + } else { + const u8 lut_118[4] = { 0xa, 0xd, 0x10, 0x14 }; + val8 = lut_118[info.clock_speed_index] - 4; + val32 |= 0xc << 28; + } + mchbar_clrsetbits32(0x114, 0xdffffcff, val32 | 0x40); + mchbar_clrsetbits32(0x118, 0x3f, val8 * 2); + + const u32 another_delay = 5625 + (info.clock_speed_index == 0 ? 1875 : 0); + const unsigned int cycle_time_ps = cycle_ps(&info); + u8 idx = 3; + while (idx * cycle_time_ps < another_delay) + idx++; + + for (channel = 0; channel < NUM_CHANNELS; channel++) { + val32 = 0x1fe; + val32 |= (idx + 1) * (1 << 17); + val32 |= val8 << 10; + val32 |= idx << 24; + val32 |= info.populated_ranks_mask[channel] << 20; + val32 |= !((info.populated_ranks_mask[channel] & 0x5) == 0x5); + mchbar_write32(0x260 + (channel << 10), val32); + } + } + for (channel = 0; channel < NUM_CHANNELS; channel++) { - mchbar_write16(0x31c + (channel << 10), 0x101); - mchbar_write16(0x360 + (channel << 10), 0x909); - mchbar_write16(0x3a4 + (channel << 10), 0x101); - mchbar_write16(0x3e8 + (channel << 10), 0x101); + const u8 clock_idx = info.clock_speed_index; + u8 val8 = clock_idx; + u32 val32 = 0x2c002c00; + if (channel == 0) { + if (info.silicon_revision == 0 || info.silicon_revision == 1) { + switch (clock_idx) { + case 0: + val8 = 8; + break; + case 1: + val8 = 2; + break; + case 2: + val8 = 9; + break; + case 3: + val8 = 10; + break; + } + } else { + val32 = 0; + } + } else { + u8 rankmask = 0x5; + rankmask &= info.populated_ranks_mask[0]; + rankmask &= info.populated_ranks_mask[1]; + if (info.silicon_revision != 1 || clock_idx < 2 || rankmask != 0x5) + val32 = 0; + else + val8 = 11; + } + const bool is_2dpc = (info.populated_ranks_mask[channel] & 0x5) == 0x5; + const u16 lut_x60[2][4] = { + { 0x101, 0x909, 0xa0a, 0x505 }, + { 0x202, 0xa0a, 0x505, 0x606 }, + }; + mchbar_write16(0x31c + (channel << 10), val8 << 8 | val8); + mchbar_write16(0x360 + (channel << 10), lut_x60[is_2dpc][clock_idx]); + mchbar_write16(0x3a4 + (channel << 10), clock_idx << 8 | clock_idx); + mchbar_write16(0x3e8 + (channel << 10), clock_idx << 8 | clock_idx); mchbar_write32(0x320 + (channel << 10), 0x29002900); - mchbar_write32(0x324 + (channel << 10), 0); + mchbar_write32(0x324 + (channel << 10), val32); mchbar_write32(0x368 + (channel << 10), 0x32003200); mchbar_write16(0x352 + (channel << 10), 0x505); mchbar_write16(0x354 + (channel << 10), 0x3c3c); @@ -3398,10 +3480,13 @@ rmw_1d0(0x21c, 0x38, 0, 6); - write_1d0(((!info.populated_ranks[1][0][0]) << 1) | ((!info. - populated_ranks[0] - [0][0]) << 0), - 0x1d1, 3, 1); + if (info.revision >= 0x10) { + u8 channel_disable_mask = 0; + channel_disable_mask |= !info.populated_ranks[0][0][0] << 0; + channel_disable_mask |= !info.populated_ranks[1][0][0] << 1; + write_1d0(channel_disable_mask, 0x1d1, 3, 1); + } + for (channel = 0; channel < NUM_CHANNELS; channel++) { mchbar_write16(0x38e + (channel << 10), 0x5f5f); mchbar_write16(0x3d2 + (channel << 10), 0x5f5f); @@ -3462,8 +3547,23 @@ write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1); } - mchbar_clrsetbits32(0x1f4, ~0, 1 << 17); // !!!! - mchbar_write32(0x1f0, 0x1d000200); + { + const u32 val0 = (info.some_delay_3_halfcycles | 1 << 8) << 9; + mchbar_clrsetbits32(0x1f4, 0x7fe81, val0); + + u8 val1 = 2; + if (info.silicon_revision == 2 || info.silicon_revision == 3) + val1 = 0; + if (info.revision < 0x10) + val1 = 0; + if (info.revision < 0x8) + val1 = info.revision_flag_1; + + const u8 val2 = info.revision_flag_1 == 0 ? 0 : 6; + const u8 val3 = info.some_delay_2_halfcycles_floor; + + mchbar_write32(0x1f0, (((0xe800 | val1) << 3 | val2) << 3 | val3) << 7); + } mchbar_setbits8(0x1f0, 1 << 0); while (mchbar_read8(0x1f0) & 1) ; @@ -3558,11 +3658,13 @@ mchbar_clrsetbits32(0x2d0, ~0xff0c01ff, 0x200000); mchbar_write16(0x6c0, 0x14a0); mchbar_clrsetbits32(0x6d0, ~0xff0000ff, 0x8000); - mchbar_write16(0x232, 1 << 3); - /* 0x40004 or 0 depending on ? */ - mchbar_clrsetbits32(0x234, 0x40004, 0x40004); + mchbar_write16(0x232, 2 + info.board_lane_delay[1] - info.max_slots_used_in_channel); + { + const u32 val32 = info.max_slots_used_in_channel == 1 ? 0x40004 : 0; + mchbar_clrsetbits32(0x234, 0x40004, val32); + } mchbar_clrsetbits32(0x34, 0x7, 5); - mchbar_write32(0x128, 0x2150d05); + mchbar_write32(0x128, ((frequency_11(&info) * 20 / 18) & 0x3ff) << 16 | 0xd05); mchbar_write8(0x12c, 0x1f); mchbar_write8(0x12d, 0x56); mchbar_write8(0x12e, 0x31); @@ -3640,8 +3742,9 @@ /* was == 1 but is common */ pci_write_config16(NORTHBRIDGE, 0xc8, 3); - write_26c(0, 0x820); - write_26c(1, 0x820); + for (channel = 0; channel < NUM_CHANNELS; channel++) + write_26c(channel, (info.clock_speed_index + 3) * 60); + mchbar_setbits32(0x130, 1 << 1); /* end */ diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h index edfce51..ea080fa 100644 --- a/src/northbridge/intel/ironlake/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -68,8 +68,11 @@ u32 delay46_ps[2]; u32 delay54_ps[2]; u8 revision_flag_1; + u8 revision_flag_2; u8 some_delay_1_cycle_floor; + u8 some_delay_2_halfcycles_floor; u8 some_delay_2_halfcycles_ceil; + u8 some_delay_3_halfcycles; u8 some_delay_3_ps_rounded; const struct ram_training *cached_training; -- To view, visit https://review.coreboot.org/c/coreboot/+/60223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e09cc67ab64699121ba75fb5473b93194d8f36f Gerrit-Change-Number: 60223 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [TESTME] nb/intel/ironlake: Improve late quickpath init
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60222 ) Change subject: [TESTME] nb/intel/ironlake: Improve late quickpath init ...................................................................... [TESTME] nb/intel/ironlake: Improve late quickpath init Change-Id: Ib7dddf3d1078a1d99c5a140793b9fdffdd73c14c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/quickpath.c 1 file changed, 78 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60222/1 diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index e13f93f..5e04c9c 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -589,9 +589,33 @@ mchbar_write32(0x18ac, 0x22222); } +static u16 get_1122_value(const struct raminfo *info, const bool is_mobile_si) +{ + if (info->revision < 0x8) { + switch (info->clock_speed_index) { + case 0: + return 0x3313; + case 1: + return 0x3011; + case 2: + return 0x2f0f; + } + } else if (!is_mobile_si) { + switch (info->clock_speed_index) { + case 0: + return 0x321a; + case 1: + return 0x2e16; + case 2: + return 0x2b13; + } + } + return 0x220a; +} + void late_quickpath_init(struct raminfo *info, const int s3resume) { - const u16 deven = pci_read_config16(NORTHBRIDGE, DEVEN); + const bool is_mobile_si = info->silicon_revision == 2 || info->silicon_revision == 3; if (s3resume && info->cached_training) { program_274265(info->cached_training); @@ -602,15 +626,15 @@ set_2dxx_series(info, s3resume); - if (!(deven & 8)) { - mchbar_clrsetbits32(0x2cb0, ~0, 0x40); + if ((pci_read_config32(NORTHBRIDGE, CAPID0 + 4) >> 11) & 1) { + mchbar_setbits32(0x2cb0, 0x1c0); } - udelay(1000); - - if (deven & 8) { - mchbar_setbits32(0xff8, 3 << 11); - mchbar_clrbits32(0x2cb0, ~0); + if (!info->uma_enabled) { + mchbar_setbits32(0x2cb0, 0x40); + } else { + mchbar_setbits32(0xff8, 1 << 11 | (1 + info->revision < 0x8) << 12); + mchbar_clrbits32(0x2cb0, 0x1c0); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e); @@ -667,18 +691,35 @@ mchbar_write32(0x1140, 0x54942404); mchbar_write32(0x1190, 0x900080a); mchbar_write16(0x11c0, 0xc40b); - mchbar_write16(0x11c2, 0x303); - mchbar_write16(0x11c4, 0x301); - mchbar_clrsetbits32(0x1190, ~0, 0x8900080a); - mchbar_write32(0x11b8, 0x70c3000); - mchbar_write8(0x11ec, 0xa); - mchbar_write16(0x1100, 0x800); - mchbar_clrsetbits32(0x11bc, ~0, 0x1e84800); - mchbar_write16(0x11ca, 0xfa); - mchbar_write32(0x11e4, 0x4e20); - mchbar_write8(0x11bc, 0xf); - mchbar_write16(0x11da, 0x19); - mchbar_write16(0x11ba, 0x470c); + if (is_mobile_si) { + mchbar_write16(0x11c2, 0x303); + mchbar_write16(0x11c4, 0x301 | (info->revision < 0x8) << 1); + } else { + mchbar_write16(0x11c2, 0x606); + mchbar_write16(0x11c4, 0x606); + } + if (info->silicon_revision == 3) + mchbar_setbits32(0x1190, 1 << 31); + + if (is_mobile_si) { + mchbar_write32(0x11b8, 0x70c3000); + mchbar_write8(0x11ec, 0xa); + mchbar_write16(0x1100, info->revision < 0x8 ? 0x3f00 : 0x800); + mchbar_clrsetbits32(0x11bc, 0xffffff << 8, 0x1e848 << 8); + mchbar_write16(0x11ca, 0xfa); + mchbar_write32(0x11e4, 0x4e20); + mchbar_write8(0x11bc, 0xf); + mchbar_write16(0x11da, 0x19); + mchbar_write16(0x11ba, 0x470c); + } else { + mchbar_write32(0x11b8, 0x5040800); + mchbar_write8(0x11ec, 0xa); + mchbar_write16(0x1100, info->revision < 0x8 ? 0x3600 : 0x2600); + mchbar_clrsetbits32(0x11bc, 0xffffff << 8, 0x186a0 << 8); + mchbar_write16(0x11ca, 0xc8); + mchbar_write32(0x11e4, 0x7d0); + mchbar_write16(0x11ba, 0x4504); + } mchbar_write32(0x1680, 0xe6ffe4ff); mchbar_write32(0x1684, 0xdeffdaff); mchbar_write32(0x1688, 0xd4ffd0ff); @@ -690,11 +731,19 @@ mchbar_write32(0x1290, 0x5000000); } - mchbar_write32(0x124c, 0x15040d00); - mchbar_write32(0x1250, 0x7f0000); - mchbar_write32(0x1254, 0x1e220004); - mchbar_write32(0x1258, 0x4000004); - mchbar_write32(0x1278, 0x0); + if (info->revision < 0x10) { + mchbar_write32(0x1250, 0xff3d0000); + mchbar_write32(0x1254, 0x0); + mchbar_write32(0x1258, 0x60001); + mchbar_write32(0x1278, 0x1000001); + mchbar_write32(0x124c, 0x8070800); + } else { + mchbar_write32(0x124c, 0x15040d00); + mchbar_write32(0x1250, 0x7f0000); + mchbar_write32(0x1254, 0x1e220004); + mchbar_write32(0x1258, 0x4000004); + mchbar_write32(0x1278, 0x0); + } mchbar_write32(0x125c, 0x0); mchbar_write32(0x1260, 0x0); mchbar_write32(0x1264, 0x0); @@ -703,7 +752,7 @@ mchbar_write32(0x1270, 0x0); mchbar_write32(0x1274, 0x0); - if (deven & 8) { + if (info->uma_enabled) { mchbar_write16(0x1214, 0x320); mchbar_write32(0x1600, 0x40000000); mchbar_clrsetbits32(0x11f4, ~0, 1 << 28); @@ -799,8 +848,9 @@ mchbar_write32(0x1560, 0x4051210); mchbar_write32(0x1564, 0x1010001); mchbar_write32(0x1568, 0x1110000); - mchbar_write16(0x1222, 0x220a); - mchbar_write16(0x123c, 0x1fc0); + mchbar_write16(0x1222, get_1122_value(info, is_mobile_si)); + if (info->revision >= 0x8) + mchbar_write16(0x123c, 0x1fc0); mchbar_write16(0x1220, 0x1388); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/60222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7dddf3d1078a1d99c5a140793b9fdffdd73c14c Gerrit-Change-Number: 60222 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [WIP, NOT WORKING YET] mb/apple/imac11_2: Add iMac 21.5-inch, Mid 2010
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Evgeny Zinoviev. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60221 ) Change subject: [WIP, NOT WORKING YET] mb/apple/imac11_2: Add iMac 21.5-inch, Mid 2010 ...................................................................... [WIP, NOT WORKING YET] mb/apple/imac11_2: Add iMac 21.5-inch, Mid 2010 Add support for the Apple 820-2784 mainboard, which can be found in the 21.5-inch Mid 2010 iMac. This system has a LGA1156 socket for Clarkdale CPUs (Lynnfield CPUs not tested), 4 DDR3 SO-DIMM slots and an Ibex Peak P55 PCH (iGPU is unused). However, even though coreboot already supports the mobile counterparts of these chips, the Ironlake northbridge code fails spectacularly: QPI initialisation renders the system so unstable that it can't even start doing raminit. Even after fixing this with [1], raminit still needs to be adapted to support Clarkdale, as well as 2 DIMMs per channel. There will be lots of magic involved. [1]: https://review.coreboot.org/60216 Change-Id: I7d5f5bacabb71d02ad3a036a82466b55ad24f8dc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/apple/imac11_2/Kconfig A src/mainboard/apple/imac11_2/Kconfig.name A src/mainboard/apple/imac11_2/Makefile.inc A src/mainboard/apple/imac11_2/acpi/ec.asl A src/mainboard/apple/imac11_2/acpi/platform.asl A src/mainboard/apple/imac11_2/acpi/superio.asl A src/mainboard/apple/imac11_2/board_info.txt A src/mainboard/apple/imac11_2/devicetree.cb A src/mainboard/apple/imac11_2/die.c A src/mainboard/apple/imac11_2/dsdt.asl A src/mainboard/apple/imac11_2/gpio.c A src/mainboard/apple/imac11_2/hda_verb.c A src/mainboard/apple/imac11_2/romstage.c 13 files changed, 385 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/60221/1 diff --git a/src/mainboard/apple/imac11_2/Kconfig b/src/mainboard/apple/imac11_2/Kconfig new file mode 100644 index 0000000..96041a5 --- /dev/null +++ b/src/mainboard/apple/imac11_2/Kconfig @@ -0,0 +1,20 @@ +if BOARD_APPLE_IMAC11_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select NORTHBRIDGE_INTEL_IRONLAKE + select SOUTHBRIDGE_INTEL_IBEXPEAK + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + default "apple/imac11_2" + +config MAINBOARD_PART_NUMBER + default "iMac11,2" + +config DRAM_RESET_GATE_GPIO + default 28 + +endif diff --git a/src/mainboard/apple/imac11_2/Kconfig.name b/src/mainboard/apple/imac11_2/Kconfig.name new file mode 100644 index 0000000..11a2451 --- /dev/null +++ b/src/mainboard/apple/imac11_2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_IMAC11_2 + bool "iMac11,2" diff --git a/src/mainboard/apple/imac11_2/Makefile.inc b/src/mainboard/apple/imac11_2/Makefile.inc new file mode 100644 index 0000000..713de4a --- /dev/null +++ b/src/mainboard/apple/imac11_2/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c +romstage-y += gpio.c + +all-y += die.c diff --git a/src/mainboard/apple/imac11_2/acpi/ec.asl b/src/mainboard/apple/imac11_2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/imac11_2/acpi/ec.asl diff --git a/src/mainboard/apple/imac11_2/acpi/platform.asl b/src/mainboard/apple/imac11_2/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/apple/imac11_2/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/apple/imac11_2/acpi/superio.asl b/src/mainboard/apple/imac11_2/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/imac11_2/acpi/superio.asl diff --git a/src/mainboard/apple/imac11_2/board_info.txt b/src/mainboard/apple/imac11_2/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/apple/imac11_2/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/apple/imac11_2/devicetree.cb b/src/mainboard/apple/imac11_2/devicetree.cb new file mode 100644 index 0000000..47f4305 --- /dev/null +++ b/src/mainboard/apple/imac11_2/devicetree.cb @@ -0,0 +1,49 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/ironlake + + device cpu_cluster 0 on + chip cpu/intel/model_2065x + device lapic 0 on end + end + end + + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe graphics + device pci 02.0 off end # iGPU + + chip southbridge/intel/ibexpeak + register "sata_port_map" = "0x3f" + + #register "gpe0_en" = "0x01800046" + #register "alt_gp_smi_en" = "0x0000" + #register "gen1_dec" = "0x040069" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1 + device pci 1c.1 on end # RP #2 + device pci 1c.2 on end # RP #3 + device pci 1c.3 on end # RP #4 + device pci 1c.4 on end # RP #5 + device pci 1c.5 on end # RP #6 + device pci 1c.6 on end # RP #7 + device pci 1c.7 on end # RP #8 + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 on end # Conventional PCI bridge + device pci 1f.0 on # LPC bridge + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.4 off end # Performance Counters + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/imac11_2/die.c b/src/mainboard/apple/imac11_2/die.c new file mode 100644 index 0000000..4a0818a --- /dev/null +++ b/src/mainboard/apple/imac11_2/die.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <northbridge/intel/ironlake/ironlake.h> +#include <types.h> + +void die_notify(void) +{ + for (unsigned int i = 0; i < 0x4000; i += 4) { + const u32 r = mchbar_read32(i); + if (r) + printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, r); + } +} diff --git a/src/mainboard/apple/imac11_2/dsdt.asl b/src/mainboard/apple/imac11_2/dsdt.asl new file mode 100644 index 0000000..6886c06 --- /dev/null +++ b/src/mainboard/apple/imac11_2/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20140108 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + #include "acpi/platform.asl" + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PCI0) + { + #include <northbridge/intel/ironlake/acpi/ironlake.asl> + + /* TBD: Remove. */ + Name(\XHCI, 0) + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + #include <northbridge/intel/ironlake/acpi/uncore.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/apple/imac11_2/gpio.c b/src/mainboard/apple/imac11_2/gpio.c new file mode 100644 index 0000000..84a9f91 --- /dev/null +++ b/src/mainboard/apple/imac11_2/gpio.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/imac11_2/hda_verb.c b/src/mainboard/apple/imac11_2/hda_verb.c new file mode 100644 index 0000000..18dc0c1 --- /dev/null +++ b/src/mainboard/apple/imac11_2/hda_verb.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */ + 0x10250379, /* Subsystem ID */ + 0, /* Number of 4 dword sets */ +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/imac11_2/romstage.c b/src/mainboard/apple/imac11_2/romstage.c new file mode 100644 index 0000000..1104045 --- /dev/null +++ b/src/mainboard/apple/imac11_2/romstage.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/ironlake/ironlake.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <stdint.h> + +/* Seems copied from Lenovo Thinkpad x201, might be wrong */ +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* Enabled, Current table lookup index, OC map */ + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 4 }, + { 1, IF1_74B, 5 }, + { 1, IF1_55F, 7 }, + { 1, IF1_55F, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, +}; + +void mainboard_pre_raminit(void) +{ +} + +void mainboard_get_spd_map(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5f5bacabb71d02ad3a036a82466b55ad24f8dc Gerrit-Change-Number: 60221 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [TESTME] nb/intel/ironlake: Fix some quickpath init magic
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Paul Menzel, Patrick Rudolph. Hello build bot (Jenkins), Paul Menzel, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60216 to look at the new patch set (#2). Change subject: [TESTME] nb/intel/ironlake: Fix some quickpath init magic ...................................................................... [TESTME] nb/intel/ironlake: Fix some quickpath init magic TO TEST: Check that Arrandale (mobile Ironlake) still works. Correct some Quickpath initialisation steps according to findings from two different Intel reference code binaries as well as MCHBAR register dump comparisons between vendor firmware and coreboot. Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init now completes successfully instead of causing hangs before raminit. Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_2065x/model_2065x.h M src/northbridge/intel/ironlake/quickpath.c M src/northbridge/intel/ironlake/raminit.c 3 files changed, 23 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60216/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Gerrit-Change-Number: 60216 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: payloads/Makefile.inc: Add warning for image built with no payload
by AreYouLoco? (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Angel Pons, Nicholas Chin. AreYouLoco? has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60025 ) Change subject: payloads/Makefile.inc: Add warning for image built with no payload ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 Gerrit-Change-Number: 60025 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: AreYouLoco? <areyouloco(a)paranoici.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin Gerrit-Comment-Date: Sun, 19 Dec 2021 12:42:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021