coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/poppy: Restore alphabetical order on Kconfig selects
by Felix Singer (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60144 to look at the new patch set (#4). Change subject: mb/google/poppy: Restore alphabetical order on Kconfig selects ...................................................................... mb/google/poppy: Restore alphabetical order on Kconfig selects Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/poppy/Kconfig 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/60144/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824 Gerrit-Change-Number: 60144 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/chili: Reuse options from Kconfig.name
by Felix Singer (Code Review) 18 Dec '21

18 Dec '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57761 ) Change subject: mb/siemens/chili: Reuse options from Kconfig.name ...................................................................... mb/siemens/chili: Reuse options from Kconfig.name Reuse the options from Kconfig.name for variant-specific selects. Change-Id: I35f51756180882d019a3ea8c555ccd18cd588f44 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57761 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/siemens/chili/Kconfig M src/mainboard/siemens/chili/Kconfig.name 2 files changed, 2 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig index a4bd180..f6e4914 100644 --- a/src/mainboard/siemens/chili/Kconfig +++ b/src/mainboard/siemens/chili/Kconfig @@ -17,13 +17,11 @@ select SOC_INTEL_CANNONLAKE_PCH_H select SOC_INTEL_COFFEELAKE -config BOARD_SIEMENS_CHILI_BASE_OPTIONS - bool +config BOARD_SIEMENS_CHILI_BASE select BOARD_SIEMENS_CHILI_COMMON select DRIVERS_UART_8250IO -config BOARD_SIEMENS_CHILI_CHILI_OPTIONS - bool +config BOARD_SIEMENS_CHILI_CHILI select BOARD_SIEMENS_CHILI_COMMON select DRIVERS_I2C_LM96000 select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/siemens/chili/Kconfig.name b/src/mainboard/siemens/chili/Kconfig.name index 1c8dab5..ac4e31e 100644 --- a/src/mainboard/siemens/chili/Kconfig.name +++ b/src/mainboard/siemens/chili/Kconfig.name @@ -4,8 +4,6 @@ config BOARD_SIEMENS_CHILI_BASE bool "-> Base board" - select BOARD_SIEMENS_CHILI_BASE_OPTIONS config BOARD_SIEMENS_CHILI_CHILI bool "-> Chili (AiO)" - select BOARD_SIEMENS_CHILI_CHILI_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/57761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f51756180882d019a3ea8c555ccd18cd588f44 Gerrit-Change-Number: 57761 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/kontron/bsl6: Reuse options from Kconfig.name
by Felix Singer (Code Review) 18 Dec '21

18 Dec '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57760 ) Change subject: mb/kontron/bsl6: Reuse options from Kconfig.name ...................................................................... mb/kontron/bsl6: Reuse options from Kconfig.name Reuse the options from Kconfig.name for variant-specific selects. Change-Id: I29ce7ef6f5137c1cf43726faed6081a04c83dea6 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57760 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/kontron/bsl6/Kconfig M src/mainboard/kontron/bsl6/Kconfig.name 2 files changed, 2 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index e4e29e0..9fae364 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -15,13 +15,11 @@ select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_I2C_NCT7802Y -config BOARD_KONTRON_BSL6_OPTIONS - bool +config BOARD_KONTRON_BSL6 select BOARD_KONTRON_BSL6_COMMON select HAVE_ACPI_RESUME -config BOARD_KONTRON_BOXER26_OPTIONS - bool +config BOARD_SIEMENS_BOXER26 select BOARD_KONTRON_BSL6_COMMON select DRIVERS_I2C_LM96000 select SECUNET_DMI diff --git a/src/mainboard/kontron/bsl6/Kconfig.name b/src/mainboard/kontron/bsl6/Kconfig.name index 90bf1c4..0f0577e 100644 --- a/src/mainboard/kontron/bsl6/Kconfig.name +++ b/src/mainboard/kontron/bsl6/Kconfig.name @@ -1,7 +1,5 @@ config BOARD_KONTRON_BSL6 bool "COMe-bSL6" - select BOARD_KONTRON_BSL6_OPTIONS config BOARD_SIEMENS_BOXER26 bool "COMe-bSL6 on Siemens/Boxer26" - select BOARD_KONTRON_BOXER26_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/57760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29ce7ef6f5137c1cf43726faed6081a04c83dea6 Gerrit-Change-Number: 57760 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [TESTME] nb/intel/ironlake: Fix some quickpath init magic
by Angel Pons (Code Review) 18 Dec '21

18 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60216 ) Change subject: [TESTME] nb/intel/ironlake: Fix some quickpath init magic ...................................................................... [TESTME] nb/intel/ironlake: Fix some quickpath init magic TO TEST: Check that Arrandale (mobile Ironlake) still works. Correct some Quickpath initialisation steps according to findings from two different Intel reference code binaries as well as MCHBAR register dump comparisons between vendor firmware and coreboot. Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init now completes successfully instead of causing hangs before raminit. Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_2065x/model_2065x.h M src/northbridge/intel/ironlake/quickpath.c M src/northbridge/intel/ironlake/raminit.c 3 files changed, 23 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60216/1 diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 9c8b180..251fd75 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,6 +20,7 @@ #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1ac #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_POWER_CTL 0x1fc diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index e0e6f66..e13f93f 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/intel/model_2065x/model_2065x.h> +#include <cpu/x86/msr.h> #include <delay.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -495,10 +497,20 @@ if (x1c04 != x1804 && x2ca8 == 0) mchbar_setbits8(0x2ca8, 1 << 0); + reg32 = 0x3000000; + if (info->silicon_revision >= 0x18 && qpi_pll_ratio <= 12) { + /* Get TDP limit in 1/8W units */ + const msr_t msr = rdmsr(MSR_TURBO_POWER_CURRENT_LIMIT); + if ((msr.lo & 0x7fff) <= 90) + reg32 = 0; + } mchbar_write32(0x18d8, 0x120000); - mchbar_write32(0x18dc, 0x30a484a); + mchbar_write32(0x18dc, reg32 | 0xa484a); + + reg32 = qpi_pll_ratio > 20 ? 8 : 16; pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0); - pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9404a | reg32 << 7); + mchbar_write32(0x18d8, 0x40000); mchbar_write32(0x18dc, 0xb000000); pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000); @@ -522,14 +534,18 @@ if (qpi_pll_ratio <= 14) reg8 = 0x33; - else if (qpi_pll_ratio <= 26) + else if (qpi_pll_ratio <= 22) reg8 = 0x42; else reg8 = 0x51; - mchbar_write32(0x1a10, reg8 << 24 | qpi_pll_ratio * 60); - mchbar_setbits32(0x18b8, 0x200); - mchbar_setbits32(0x1918, 0x300); + info->fsb_frequency = qpi_pll_ratio * 15; + mchbar_write32(0x1a10, reg8 << 24 | info->fsb_frequency); + + if (info->silicon_revision == 2 || info->silicon_revision == 3) { + mchbar_setbits32(0x18b8, 0x200); + mchbar_setbits32(0x1918, 0x300); + } if (info->revision > 0x17) mchbar_setbits32(0x18b8, 0xc00); diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 72c3028..38ffa19 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3157,7 +3157,6 @@ info.last_500_command[0] = 0; info.last_500_command[1] = 0; - info.fsb_frequency = 135 * 2; info.board_lane_delay[0] = 0x14; info.board_lane_delay[1] = 0x07; info.board_lane_delay[2] = 0x07; @@ -3393,7 +3392,6 @@ write_1d0(0x4, 0x151, 4, 1); write_1d0(0, 0x142, 3, 1); - rdmsr(0x1ac); // !!!! write_500(&info, 1, 1, 0x6b3, 4, 1); write_500(&info, 1, 1, 0x6cf, 4, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/60216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Gerrit-Change-Number: 60216 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/starlabs: Add LabTop Mk IV
by Andy Pont (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Sean Rhodes, Angel Pons. Andy Pont has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mainboard/starlabs: Add LabTop Mk IV ...................................................................... Patch Set 67: (1 comment) File src/mainboard/starlabs/labtop/variants/cml/gpio.c: https://review.coreboot.org/c/coreboot/+/58428/comment/97ea62ce_225322b1 PS66, Line 14: PAD_CFG_GPI(GPP_H6, NONE, PLTRST), : PAD_CFG_GPI(GPP_H7, NONE, PLTRST), > Am curious about these as well. GPP_E22, E23, H6, H7 are connected to pull-up or pull-down resistors which give the firmware an indication as to which memory type is fitted. See comments in romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 67 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Dec 2021 17:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Update Vbt
by Andy Pont (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Sean Rhodes, Paul Menzel. Andy Pont has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59727 ) Change subject: mb/starlabs/labtop: Update Vbt ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Patchset: PS8: It can have a +1 from me as I presume it does what it says on the tin! -- To view, visit https://review.coreboot.org/c/coreboot/+/59727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec Gerrit-Change-Number: 59727 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 18 Dec 2021 16:53:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
by build bot (Jenkins) (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, David Guckian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36607 ) Change subject: mb/teleplatforms/D4E4S16P8: Configure ast25xx bootstraps ...................................................................... Patch Set 16: Verified+1 (3 comments) File src/mainboard/teleplatforms/D4E4S16P8/ast25xx.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135803): https://review.coreboot.org/c/coreboot/+/36607/comment/b36f4c3f_dce28778 PS16, Line 44: printk(BIOS_INFO, "ast25xx: disable protection status: @ 0x%p 0x%08x\n", scu_protection, locks); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135803): https://review.coreboot.org/c/coreboot/+/36607/comment/55b07322_6a88f68d PS16, Line 47: printk(BIOS_INFO, "ast25xx: scu70_hwtrap current bits: @ 0x%p 0x%08x\n", scu_hwtrap, straps); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135803): https://review.coreboot.org/c/coreboot/+/36607/comment/98a15ad5_8e0248ca PS16, Line 76: printk(BIOS_INFO, "ast25xx: p2p_bridge0: 0x%x; p2p_bridge1: 0x%x\n", p2p_bridge0, p2p_bridge1); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/36607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92195969419f9c38845cb67f294fdab33fb481af Gerrit-Change-Number: 36607 Gerrit-PatchSet: 16 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: David Guckian <d.guckian20(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: David Guckian <d.guckian20(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Dec 2021 16:46:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Add more Westmere/Ironlake device IDs
by Angel Pons (Code Review) 18 Dec '21

18 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60215 ) Change subject: util/inteltool: Add more Westmere/Ironlake device IDs ...................................................................... util/inteltool: Add more Westmere/Ironlake device IDs Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/60215/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 14f6851..9e782ef 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -81,7 +81,11 @@ /* Host bridges /DRAM controllers integrated in CPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D, + "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M, + "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048, "1st generation (Westmere family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D, "2nd generation (Sandy Bridge family) Core Processor (Desktop)" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 97091c5..41dd4d1 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -280,7 +280,9 @@ /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ -#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D 0x0040 /* Clarkdale (Westmere Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M 0x0044 /* Arrandale (Westmere Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048 0x0048 /* Unknown Westmere */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 36d1197..df13d81 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -189,7 +189,9 @@ mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; - case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ @@ -260,7 +262,9 @@ switch (nb->device_id) { - case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048: printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1); dump_timings (); if (dump_spd_file != NULL) diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index d392c28..8e21b51 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -349,7 +349,9 @@ dmi_registers = nehalem_dmi_registers; size = ARRAY_SIZE(nehalem_dmi_registers); break; - case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b Gerrit-Change-Number: 60215 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add CRB using intel/denverton_ns
by Kyösti Mälkki (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Dmitry Ponamorev, Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, King Sumo. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add CRB using intel/denverton_ns ...................................................................... Patch Set 24: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57194/comment/76beeed0_daa970a0 PS20, Line 7: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/57194/comment/5a64df61_874543e9 PS20, Line 10: teleplatforms D4E4S16P8 motherboard. > As there is no documentation included in the change-set, please summarize, what the board is/uses. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 24 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Dec 2021 16:36:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Fix comment about early GPIOs
by Tim Wawrzynczak (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Tim Crawford, Maxim Polyakov, Jeremy Soller, Angel Pons, Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60210 ) Change subject: mainboard: Fix comment about early GPIOs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Gerrit-Change-Number: 60210 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sat, 18 Dec 2021 16:36:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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