coreboot-gerrit December 2021

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Change in coreboot[master]: util/cbfstool: Remove redundant endian.h include
by Alex James (Code Review) 19 Dec '21

19 Dec '21

Alex James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60228 ) Change subject: util/cbfstool: Remove redundant endian.h include ...................................................................... util/cbfstool: Remove redundant endian.h include flashmap/fmap.c includes commonlib/bsd/sysincludes.h, which already includes the necessary header for endian(3) functions (endian.h on Linux and sys/endian.h on FreeBSD). This also resolves a compilation error on macOS (tested on 10.5.7), as macOS does not provide endian.h. Change-Id: I0cb17eacd253605b75db8cf734e71ca3fe24ad6c Signed-off-by: Alex James <theracermaster(a)gmail.com> --- M util/cbfstool/flashmap/fmap.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/60228/1 diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index cb67b46..7010dbc 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause or GPL-2.0-only */ #include <ctype.h> -#include <endian.h> #include <stdlib.h> #include <stdio.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cb17eacd253605b75db8cf734e71ca3fe24ad6c Gerrit-Change-Number: 60228 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib: Add endian definitions for macOS
by Alex James (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Alex James. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60219 to look at the new patch set (#2). Change subject: commonlib: Add endian definitions for macOS ...................................................................... commonlib: Add endian definitions for macOS macOS has never defined the usual endian(3)/byteorder(9) byte-swapping functions. This change implements these byte-swapping functions using the OSSwap functions, which provide identical functionality. This was tested on macOS 10.15.7. Change-Id: I44d59869a4420030f3ce26118175304c680d57a1 Signed-off-by: Alex James <theracermaster(a)gmail.com> --- M src/commonlib/bsd/include/commonlib/bsd/sysincludes.h 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/60219/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44d59869a4420030f3ce26118175304c680d57a1 Gerrit-Change-Number: 60219 Gerrit-PatchSet: 2 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: xcompile: Support i686-elf toolchains
by Alex James (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Martin Roth, Alex James. Hello build bot (Jenkins), Martin Roth, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60218 to look at the new patch set (#2). Change subject: xcompile: Support i686-elf toolchains ...................................................................... xcompile: Support i686-elf toolchains This allows i686-elf toolchains (including i686-elf-gcc [1] and i686-elf-binutils [2]) distributed by Homebrew) to be detected. [1]: https://formulae.brew.sh/formula/i686-elf-gcc [2]: https://formulae.brew.sh/formula/i686-elf-binutils Change-Id: Ibdf2cdd8b244822740c03935747184ebc5ca1512 Signed-off-by: Alex James <theracermaster(a)gmail.com> --- M util/xcompile/xcompile 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/60218/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdf2cdd8b244822740c03935747184ebc5ca1512 Gerrit-Change-Number: 60218 Gerrit-PatchSet: 2 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [DO NOT SUBMIT] nb/intel/ironlake: Debugging attempts
by build bot (Jenkins) (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60227 ) Change subject: [DO NOT SUBMIT] nb/intel/ironlake: Debugging attempts ...................................................................... Patch Set 1: (17 comments) File src/northbridge/intel/ironlake/raminit.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/326d674b_96d96386 PS1, Line 3079: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/551482fc_3790a483 PS1, Line 3080: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/dfc1a531_0f0468a0 PS1, Line 3081: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/dc0422ae_210a714f PS1, Line 3084: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/1fa491b4_cce3e788 PS1, Line 3091: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/13862554_a2e7e247 PS1, Line 3092: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/fc9680f6_e8b51928 PS1, Line 3093: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/3a16e804_abc23a1b PS1, Line 3096: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/6a910378_2bd65117 PS1, Line 3103: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/87cd3917_6f38db33 PS1, Line 3104: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/a73d920a_e8f68b2e PS1, Line 3105: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/b92c7dba_96899d88 PS1, Line 3108: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/e9367fac_86982f3d PS1, Line 3115: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/51ac47a9_65af078c PS1, Line 3116: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/9085b6e1_42f2978d PS1, Line 3117: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/5dd9036f_48629368 PS1, Line 3120: { Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135841): https://review.coreboot.org/c/coreboot/+/60227/comment/f5e6c034_4f42d520 PS1, Line 3128: if (0)memcpy(&info->training.lane_timings, &lane_timings, sizeof(lane_timings)); trailing statements should be on next line -- To view, visit https://review.coreboot.org/c/coreboot/+/60227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e00329e45057ea07c24f3a034fd3bd5575f8cf Gerrit-Change-Number: 60227 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 19 Dec 2021 20:32:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfstool: Fix compilation on macOS
by Alex James (Code Review) 19 Dec '21

19 Dec '21

Alex James has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60220 ) Change subject: cbfstool: Fix compilation on macOS ...................................................................... Abandoned Going to split into multiple changes -- To view, visit https://review.coreboot.org/c/coreboot/+/60220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5997d6d00e12f9f960550e72333ec354593501c Gerrit-Change-Number: 60220 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [DO NOT SUBMIT] nb/intel/ironlake: Debugging attempts
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60227 ) Change subject: [DO NOT SUBMIT] nb/intel/ironlake: Debugging attempts ...................................................................... [DO NOT SUBMIT] nb/intel/ironlake: Debugging attempts Change-Id: I41e00329e45057ea07c24f3a034fd3bd5575f8cf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/quickpath.c M src/northbridge/intel/ironlake/raminit.c 2 files changed, 93 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/60227/1 diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index 5e04c9c..bca81a1 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -191,6 +191,7 @@ delay_f_cycles = div_roundup(2500 - delay_e_over_cycle_ps, 2 * halfcycle_ps(info)); + if (delay_f_cycles > delay_e_cycles) { info->delay46_ps[channel] = delay_e_ps; delay_e_cycles = 0; @@ -239,7 +240,7 @@ (training->reg274265[channel][0] << 16) | training->reg274265[channel][1]); mchbar_write16((channel << 10) + 0x265, - training->reg274265[channel][2] << 8); + training->reg274265[channel][2] << 8); /* read and merging write win */ } if (training->reg2ca9_bit0) mchbar_setbits8(0x2ca9, 1 << 0); diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index bac8832..951e24f 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -309,7 +309,8 @@ slot, rank), 9, 0); - gav(get_580(channel, ((i + 1) << 2) | (rank << 5))); + u16 result = get_580(channel, ((i + 1) << 2) | (rank << 5)); + printk(BIOS_DEBUG, "i = %d, result = 0x%04x\n", i, result); } toggle_1d0_142_5ff(); @@ -337,6 +338,15 @@ return res; } + +static u32 egav_real(int line, u32 in) +{ + printk(BIOS_DEBUG, "%d: EGAV: %x\n", line, in); + return in; +} + +#define egav(x) egav_real(__LINE__, (x)) + static void config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank) { @@ -351,12 +361,12 @@ else add = 0; if (!s3resume) - gav(rw_test(rank + add)); + egav(rw_test(rank + add)); program_timings(info, 0x00, channel, slot, rank); if (!s3resume) - gav(rw_test(rank + add)); + egav(rw_test(rank + add)); if (!s3resume) - gav(rw_test(rank + add)); + egav(rw_test(rank + add)); write_1d0(0, 0x142, 3, 1); write_1d0(0, 0x103, 6, 1); @@ -764,12 +774,11 @@ else some_delay_1_cycle_floor--; info->some_delay_1_cycle_floor = some_delay_1_cycle_floor; + const int some_delay_1_ps_ceil = (some_delay_1_cycle_ceil - 1) * cycle_ps(info); if (info->revision_flag_1) some_delay_2_ps = halfcycle_ps(info) >> 6; - some_delay_2_ps += - MAX(some_delay_1_ps - 30, - 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) + - 375; + + some_delay_2_ps += MAX(some_delay_1_ps - 30, some_delay_1_ps_ceil + 1000) + 375; some_delay_3_ps = halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info); info->some_delay_3_halfcycles = 0; @@ -1111,8 +1120,7 @@ high_multiplier = 0; some_delay_ns = 200; some_delay_3_half_cycles = 4; - cas_latency_shift = info->silicon_revision == 0 - || info->silicon_revision == 1 ? 1 : 0; + cas_latency_shift = info->silicon_revision == 0 || info->silicon_revision == 1 ? 1 : 0; if (info->revision < 8) { some_delay_ns = 600; cas_latency_shift = 0; @@ -1449,10 +1457,10 @@ write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1); } -static void dump_timings(struct raminfo *info) +static void dump_timings_real(struct raminfo *info, int line) { int channel, slot, rank, lane, i; - printk(RAM_SPEW, "Timings:\n"); + printk(RAM_SPEW, "Timings %d:\n", line); FOR_POPULATED_RANKS { printk(RAM_SPEW, "channel %d, slot %d, rank %d\n", channel, slot, rank); @@ -1477,6 +1485,8 @@ info->training.reg_10b); } +#define dump_timings(x) dump_timings_real(x, __LINE__) + /* Read timings and other registers that need to be restored verbatim and put them to CBMEM. */ @@ -2126,11 +2136,14 @@ } } + printk(BIOS_DEBUG, "reg1b3\tresult\n"); + for (reg1b3 = 0; reg1b3 < 0x30 && !validate_state(state); reg1b3++) { u8 failmask = 0; write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1); write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1); failmask = check_testing(info, total_rank, 0); + printk(BIOS_DEBUG, "%d\t0x%02x\n", reg1b3, failmask); mchbar_setbits32(0xfb0, 3 << 16); do_fsm(state, count, failmask, 5, 47, lower_usable, upper_usable, reg1b3); @@ -2613,15 +2626,21 @@ u8 reg178; int count = 0, sum = 0; + printk(BIOS_DEBUG, "r178\t 0 1 2 3 4 5 6 7\t 0 1 2 3 4 5 6 7"); + for (reg178 = reg178_min[info->clock_speed_index]; reg178 < reg178_max[info->clock_speed_index]; reg178 += reg178_step[info->clock_speed_index]) { margin[reg178] = -1; + printk(BIOS_DEBUG, "\n%d", reg178); FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { int curmargin = timings[reg178][channel][slot][rank][lane].largest - timings[reg178][channel][slot][rank][lane]. smallest + 1; + if (lane == 0) + printk(BIOS_DEBUG, "\t"); + printk(BIOS_DEBUG, "% 4d", curmargin); if (curmargin < margin[reg178]) margin[reg178] = curmargin; } @@ -2632,6 +2651,7 @@ count += weight; } } + printk(BIOS_DEBUG, "\n"); dump_timings(info); if (count == 0) die("Couldn't discover DRAM timings (3)\n"); @@ -3054,6 +3074,65 @@ if (info->revision >= 8) read_4090(info); + const u16 lane_timings[4][2][2][2][9] = { + { + { + { + { + 0x15, 0x15, 0x15, 0x14, 0x15, 0x14, 0x15, 0x15, 0x15, + }, + { + 0x16, 0x16, 0x14, 0x13, 0x16, 0x14, 0x15, 0x16, 0x15, + }, + }, + }, + }, + { + { + { + { + 0xe0, 0xe8, 0xc6, 0xf5, 0x73, 0xad, 0x91, 0x9e, 0x100, + }, + { + 0xe0, 0xe8, 0xc0, 0xf1, 0x71, 0xad, 0x91, 0x9f, 0x100, + }, + }, + }, + }, + { + { + { + { + 0xa7, 0xb5, 0x98, 0xd3, 0x50, 0x82, 0x6d, 0x72, 0x97, + }, + { + 0xa6, 0xb6, 0x97, 0xcf, 0x4b, 0x7e, 0x6b, 0x73, 0x97, + }, + }, + }, + }, + { + { + { + { + 0xc1, 0xcc, 0xb3, 0xee, 0x6b, 0x9c, 0x85, 0x8d, 0x97, + }, + { + 0xc0, 0xcd, 0xb2, 0xea, 0x66, 0x98, 0x84, 0x8d, 0x97, + }, + }, + }, + }, + }; + + if (0)memcpy(&info->training.lane_timings, &lane_timings, sizeof(lane_timings)); + + for (int channel = 0; channel < NUM_CHANNELS; channel++) + for (int slot = 0; slot < NUM_SLOTS; slot++) + for (int rank = 0; rank < NUM_RANKS; rank++) + if (info->populated_ranks[channel][slot][rank]) + program_timings(info, 0, channel, slot, rank); + if (!try_cached_training(info)) do_ram_training(info); if ((info->silicon_revision == 2 || info->silicon_revision == 3) -- To view, visit https://review.coreboot.org/c/coreboot/+/60227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e00329e45057ea07c24f3a034fd3bd5575f8cf Gerrit-Change-Number: 60227 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] nb/intel/ironlake: Even more magic
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60226 ) Change subject: [TESTME] nb/intel/ironlake: Even more magic ...................................................................... [TESTME] nb/intel/ironlake: Even more magic Change-Id: Ia2c3b47d908cfed49757c0449aeebf05dccbc799 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 93 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/60226/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 668d610..bac8832 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -19,6 +19,7 @@ #include <spd.h> #include <timestamp.h> #include <cpu/x86/mtrr.h> +#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <mrc_cache.h> @@ -424,6 +425,11 @@ write_1d0((v & and) | or, addr, split, 1); } +static void or_1d0(u16 addr, u32 or, int bits) +{ + rmw_1d0(addr, ~0, or, bits); +} + static int find_highest_bit_set(u16 val) { int i; @@ -1112,19 +1118,17 @@ cas_latency_shift = 0; } { - int speed_bit; - speed_bit = - ((info->clock_speed_index > 1 - || (info->silicon_revision != 2 - && info->silicon_revision != 3))) ^ (info->revision >= - 0x10); - write_500(info, 0, speed_bit | ((!info->use_ecc) << 1), 0x60e, - 3, 1); - write_500(info, 1, speed_bit | ((!info->use_ecc) << 1), 0x60e, - 3, 1); - if (info->revision >= 0x10 && info->clock_speed_index <= 1 - && (info->silicon_revision == 2 - || info->silicon_revision == 3)) + u8 speed_bit = 0; + if (info->clock_speed_index <= 1) { + if (info->silicon_revision == 2 || info->silicon_revision == 3) + speed_bit = 1; + } + if (info->revision < 0x10) + speed_bit = !speed_bit; + + write_500(info, 0, speed_bit | !info->use_ecc << 1, 0x60e, 3, 1); + write_500(info, 1, speed_bit | !info->use_ecc << 1, 0x60e, 3, 1); + if (info->revision >= 0x10 && speed_bit) rmw_1d0(0x116, 5, 2, 4); } mchbar_write32(0x120, 1 << (info->max_slots_used_in_channel + 28) | 0x188e7f9f); @@ -1215,27 +1219,30 @@ cas_latency_derived++; for (channel = 0; channel < NUM_CHANNELS; channel++) { mchbar_write32(0x240 + (channel << 10), - ((info->clock_speed_index == 0) * 0x11000) | - 0x1002100 | (2 + info->clock_speed_index) << 4 | - (info->cas_latency - 3)); - write_500(info, channel, (info->clock_speed_index << 1) | 1, + (info->cas_latency - 3) | + (2 + info->clock_speed_index) << 4 | + ((info->clock_speed_index == 0) + 2) << 12 | + (info->clock_speed_index == 0) << 16 | + 0x1000100); + write_500(info, channel, info->clock_speed_index * 2 + 1, 0x609, 6, 1); write_500(info, channel, info->clock_speed_index + 2 * info->cas_latency - 7, 0x601, 6, 1); mchbar_write32(0x250 + (channel << 10), - (lane_3_delay + info->clock_speed_index + 9) << 6 | - info->board_lane_delay[7] << 2 | - info->board_lane_delay[4] << 16 | - info->board_lane_delay[1] << 25 | + (lane_3_delay + info->clock_speed_index + 9) << 6 | /* write to pchg */ + info->board_lane_delay[7] << 2 | /* read to precharge */ + info->board_lane_delay[4] << 16 | /* refresh to activate */ + info->board_lane_delay[1] << 25 | /* precharge to activate */ info->board_lane_delay[1] << 29 | 1); mchbar_write32(0x254 + (channel << 10), info->board_lane_delay[1] >> 3 | - (info->board_lane_delay[8] + 4 * info->use_ecc) << 6 | - 0x80 | info->board_lane_delay[6] << 1 | - info->board_lane_delay[2] << 28 | - cas_latency_derived << 16 | 0x4700000); + (info->board_lane_delay[8] + 2 + 4 * info->use_ecc) << 6 | /* tFAW */ + info->board_lane_delay[6] << 1 | /* activate to activate */ + info->board_lane_delay[2] << 28 | /* activate to write */ + cas_latency_derived << 16 | /* read to write */ + 0x4700000); mchbar_write32(0x258 + (channel << 10), (info->board_lane_delay[5] + info->clock_speed_index + 9) << 12 | (info->clock_speed_index + 12 - info->cas_latency) << 8 | @@ -3177,12 +3184,12 @@ info.board_lane_delay[8] = 0x10; */ info.board_lane_delay[0] = 0x18; - info.board_lane_delay[1] = 0x07; - info.board_lane_delay[2] = 0x07; - info.board_lane_delay[3] = 0x08; + info.board_lane_delay[1] = 0x09; + info.board_lane_delay[2] = 0x09; + info.board_lane_delay[3] = 0x0a; info.board_lane_delay[4] = 0x4a; - info.board_lane_delay[5] = 0x04; - info.board_lane_delay[6] = 0x04; + info.board_lane_delay[5] = 0x05; + info.board_lane_delay[6] = 0x04 | 1 << 7; /* HACK FOR maxact_dischk */ info.board_lane_delay[7] = 0x05; info.board_lane_delay[8] = 0x10; @@ -3463,7 +3470,7 @@ mchbar_write16(0x3e8 + (channel << 10), clock_idx << 8 | clock_idx); mchbar_write32(0x320 + (channel << 10), 0x29002900); mchbar_write32(0x324 + (channel << 10), val32); - mchbar_write32(0x368 + (channel << 10), 0x32003200); + mchbar_write32(0x368 + (channel << 10), is_2dpc ? 0x07000700 : 0x32003200); mchbar_write16(0x352 + (channel << 10), 0x505); mchbar_write16(0x354 + (channel << 10), 0x3c3c); mchbar_write16(0x356 + (channel << 10), 0x1040); @@ -3472,9 +3479,50 @@ mchbar_write16(0x422 + (channel << 10), 0x1040); } - write_1d0(0x4, 0x151, 4, 1); - write_1d0(0, 0x142, 3, 1); - rdmsr(0x1ac); // !!!! + { + u32 local_20; + if (info.revision >= 0x10) + local_20 = 4; + else if (info.revision >= 0x8) + local_20 = 0; + else if (1 /* some unknown checks */) + local_20 = 6; + else + local_20 = 2; + + write_1d0(local_20, 0x151, 4, 1); + write_1d0(0, 0x142, 3, 1); + + if (info.revision >= 0x18) { + /* Get TDP limit in 1/8W units */ + const msr_t msr = rdmsr(MSR_TURBO_POWER_CURRENT_LIMIT); + if ((msr.lo & 0x7fff) < 145) { + or_1d0(0x132, 1 << 2, 5); + or_1d0(0x132, 1 << 1, 5); + or_1d0(0xce, 1 << 3, 6); + or_1d0(0x320, 1 << 3, 6); + or_1d0(0x132, 1 << 0, 5); + or_1d0(0xd6, 1 << 4, 6); + or_1d0(0x328, 1 << 4, 6); + or_1d0(0x11c, 1 << 2, 4); + or_1d0(0x11c, 1 << 1, 4); + or_1d0(0x11c, 1 << 0, 4); + or_1d0(0xd6, 1 << 3, 6); + or_1d0(0x328, 1 << 3, 6); + or_1d0(0x132, 1 << 3, 5); + or_1d0(0x132, 1 << 3, 5); + or_1d0(0xce, 1 << 4, 6); + or_1d0(0x132, 1 << 3, 5); + or_1d0(0xce, 1 << 4, 6); + or_1d0(0x11c, 1 << 3, 4); + or_1d0(0x11c, 1 << 3, 4); + or_1d0(0x11c, 1 << 3, 4); + or_1d0(0xce, 1 << 4, 6); + or_1d0(0x320, 1 << 4, 6); + } + } + } + write_500(&info, 1, 1, 0x6b3, 4, 1); write_500(&info, 1, 1, 0x6cf, 4, 1); @@ -3667,7 +3715,13 @@ mchbar_write32(0x128, ((frequency_11(&info) * 20 / 18) & 0x3ff) << 16 | 0xd05); mchbar_write8(0x12c, 0x1f); mchbar_write8(0x12d, 0x56); - mchbar_write8(0x12e, 0x31); + { + u8 val8 = 3; + if (info.clock_speed_index > 0 /* || unknown check */) + val8 = 0; + + mchbar_write8(0x12e, (val8 | 0xc) << 2 | info.max_slots_used_in_channel); + } mchbar_write8(0x12f, 0); mchbar_write8(0x271, 1 << 1); mchbar_write8(0x671, 1 << 1); @@ -3675,7 +3729,11 @@ for (channel = 0; channel < NUM_CHANNELS; channel++) mchbar_write32(0x294 + (channel << 10), (info.populated_ranks_mask[channel] & 3) << 16); + mchbar_clrsetbits32(0x134, ~0xfc01ffff, 0x10000); + + mdelay(1); + mchbar_clrsetbits32(0x134, ~0xfc85ffff, 0x850000); for (channel = 0; channel < NUM_CHANNELS; channel++) mchbar_clrsetbits32(0x260 + (channel << 10), 0xf << 20, 1 << 27 | -- To view, visit https://review.coreboot.org/c/coreboot/+/60226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2c3b47d908cfed49757c0449aeebf05dccbc799 Gerrit-Change-Number: 60226 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Use `NUM_CHANNELS` macro
by Angel Pons (Code Review) 19 Dec '21

19 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60225 ) Change subject: nb/intel/ironlake: Use `NUM_CHANNELS` macro ...................................................................... nb/intel/ironlake: Use `NUM_CHANNELS` macro Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/60225/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 72c3028..9277477 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -792,7 +792,7 @@ info->max_slots_used_in_channel = 2; else info->max_slots_used_in_channel = 1; - for (channel = 0; channel < 2; channel++) + for (channel = 0; channel < NUM_CHANNELS; channel++) mchbar_write32(0x244 + (channel << 10), ((info->revision < 8) ? 1 : 0x200) | ((2 - info->max_slots_used_in_channel) << 17) | -- To view, visit https://review.coreboot.org/c/coreboot/+/60225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7 Gerrit-Change-Number: 60225 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: payloads/Makefile.inc: Add warning for image built with no payload
by Nico Huber (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Angel Pons, Nicholas Chin. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60025 ) Change subject: payloads/Makefile.inc: Add warning for image built with no payload ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 Gerrit-Change-Number: 60025 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: AreYouLoco? <areyouloco(a)paranoici.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin Gerrit-Comment-Date: Sun, 19 Dec 2021 16:51:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/Makefile.inc: Add warning for image built with no payload
by Nico Huber (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Angel Pons, Nicholas Chin. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60025 ) Change subject: payloads/Makefile.inc: Add warning for image built with no payload ...................................................................... Patch Set 3: (1 comment) File payloads/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60025/comment/575ab790_ba08ba15 PS1, Line 60: printf "You can use cbfstool to add a payload to the image.\n\n" > Tweaked lines and rebased onto master Thanks :) -- To view, visit https://review.coreboot.org/c/coreboot/+/60025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 Gerrit-Change-Number: 60025 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: AreYouLoco? <areyouloco(a)paranoici.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin Gerrit-Comment-Date: Sun, 19 Dec 2021 16:49:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nicholas Chin Gerrit-MessageType: comment

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