coreboot-gerrit December 2021

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Change in coreboot[master]: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP
by Usha P (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Anilkumar N, Maulik V Vaghela, Kangheui Won, Tim Wawrzynczak, Reka Norman, Krishna P Bhat D. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60193 ) Change subject: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP ...................................................................... Patch Set 2: (1 comment) File src/mainboard/intel/adlrvp/spd/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60193/comment/ab33a59b_93f92652 PS1, Line 10: SPD_SOURCES += adlrvp_n_lp5 # 0b007 > Can you please capture in commit msg? […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Gerrit-Change-Number: 60193 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 07:40:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP
by Usha P (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Anilkumar N, Kangheui Won, Tim Wawrzynczak, Reka Norman, Krishna P Bhat D. Usha P has uploaded a new patch set (#2) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/60193 ) Change subject: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP ...................................................................... mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP Add support for Alder lake N LP5 RVP with board ID 0x7. Since SPD index 7 is unused earlier, ADL-N will use it. Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex 5 files changed, 100 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/60193/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Gerrit-Change-Number: 60193 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP
by Maulik V Vaghela (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Anilkumar N, Kangheui Won, Tim Wawrzynczak, Reka Norman, Krishna P Bhat D. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60193 ) Change subject: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/intel/adlrvp/spd/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60193/comment/b2132dde_484f03e3 PS1, Line 10: SPD_SOURCES += adlrvp_n_lp5 # 0b007 Can you please capture in commit msg? We're utilizing SPD index 7 since it's been unused earlier and ADL-N will use it. -- To view, visit https://review.coreboot.org/c/coreboot/+/60193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Gerrit-Change-Number: 60193 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 07:29:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cret: Generate new SPD ID for new memory parts
by Dtrain Hsu (Code Review) 20 Dec '21

20 Dec '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58412 to look at the new patch set (#3). Change subject: mb/google/dedede/var/cret: Generate new SPD ID for new memory parts ...................................................................... mb/google/dedede/var/cret: Generate new SPD ID for new memory parts Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 BUG=b:203837656 BRANCH=dedede TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784 --- M src/mainboard/google/dedede/variants/cret/memory/Makefile.inc M src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/58412/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784 Gerrit-Change-Number: 58412 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/cret: Generate new SPD ID for new memory parts
by Dtrain Hsu (Code Review) 20 Dec '21

20 Dec '21

Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58412 ) Change subject: mb/google/dedede/var/cret: Generate new SPD ID for new memory parts ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/58412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784 Gerrit-Change-Number: 58412 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 20 Dec 2021 07:22:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb: Remove dot from end of non-sentence comment
by Paul Menzel (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Tim Crawford, Patrick Rudolph, Jeremy Soller, Christian Walter. Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60248 ) Change subject: mb: Remove dot from end of non-sentence comment ...................................................................... mb: Remove dot from end of non-sentence comment Run the command below to fix all occurrences. $ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,' Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/google/glados/variants/asuka/include/variant/gpio.h M src/mainboard/google/glados/variants/caroline/include/variant/gpio.h M src/mainboard/google/glados/variants/cave/include/variant/gpio.h M src/mainboard/google/glados/variants/chell/include/variant/gpio.h M src/mainboard/google/glados/variants/glados/include/variant/gpio.h M src/mainboard/google/glados/variants/lars/include/variant/gpio.h M src/mainboard/google/glados/variants/sentry/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h M src/mainboard/intel/kunimitsu/gpio.h M src/mainboard/intel/saddlebrook/gpio.h M src/mainboard/prodrive/hermes/gpio.c M src/mainboard/starlabs/labtop/variants/tgl/gpio.c M src/mainboard/system76/lemp9/gpio.h 16 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/60248/1 diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index 3ee5532..758b7cc 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -214,7 +214,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index 7f8787c..fe31102 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -231,7 +231,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index 0eb7de7..e96a78a 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -223,7 +223,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index e152862..3260472 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -217,7 +217,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index 248e7dd..b812fb7 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -220,7 +220,7 @@ /* LANPHYC */ /* GPD11 */ }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index ee55512..7cf56aa 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -208,7 +208,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 06f6cd8..10291b0 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -216,7 +216,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h index aaec3eb..fb47e6f 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -257,7 +257,7 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h index 26eb1d9..11a6b82 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h @@ -193,7 +193,7 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index d2e76d9..9c252e2 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -193,7 +193,7 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index 44997c7..1c112df 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -159,7 +159,7 @@ }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index a436d8f..c4628f2 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -217,7 +217,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h index b012462..da9c27e 100644 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ b/src/mainboard/intel/saddlebrook/gpio.h @@ -245,7 +245,7 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ }; diff --git a/src/mainboard/prodrive/hermes/gpio.c b/src/mainboard/prodrive/hermes/gpio.c index f228ef8..5cb901d 100644 --- a/src/mainboard/prodrive/hermes/gpio.c +++ b/src/mainboard/prodrive/hermes/gpio.c @@ -369,7 +369,7 @@ }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { /* Get PCIe out of reset */ PAD_CFG_GPO(GPP_K0, 1, DEEP), /* PERST_PCH_SLOTS_n */ diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c index 81f6cb7..a0fc12c 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c @@ -7,7 +7,7 @@ * using the stock BIOS and with coreboot. */ -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h index 60cc7b6..518a500 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/lemp9/gpio.h @@ -10,7 +10,7 @@ /* Name format: <pad name> / <net/pin name in schematics> */ -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Gerrit-Change-Number: 60248 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb: Add space before closing comment block keyword
by Paul Menzel (Code Review) 20 Dec '21

20 Dec '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60247 ) Change subject: mb: Add space before closing comment block keyword ...................................................................... mb: Add space before closing comment block keyword Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/blipper/gpio.c M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/bugzzy/gpio.c M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/galtic/gpio.c M src/mainboard/google/dedede/variants/gooey/gpio.c M src/mainboard/google/dedede/variants/haboki/gpio.c M src/mainboard/google/dedede/variants/kracko/gpio.c M src/mainboard/google/dedede/variants/metaknight/gpio.c M src/mainboard/google/dedede/variants/pirika/gpio.c M src/mainboard/google/dedede/variants/sasuke/gpio.c M src/mainboard/google/dedede/variants/sasukette/gpio.c M src/mainboard/google/dedede/variants/storo/gpio.c M src/mainboard/google/dedede/variants/waddledee/gpio.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c 24 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/60247/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 3bee320..e1b920a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ /* A0 : ESPI_IO0 */ diff --git a/src/mainboard/google/dedede/variants/blipper/gpio.c b/src/mainboard/google/dedede/variants/blipper/gpio.c index 6af1ed7..8b754ee 100644 --- a/src/mainboard/google/dedede/variants/blipper/gpio.c +++ b/src/mainboard/google/dedede/variants/blipper/gpio.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* C18 : AP_I2C_EMR_SDA */ PAD_NC(GPP_C18, NONE), diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index 123a3bb..5085917 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/bugzzy/gpio.c b/src/mainboard/google/dedede/variants/bugzzy/gpio.c index a218c5e..16cf61b 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/gpio.c +++ b/src/mainboard/google/dedede/variants/bugzzy/gpio.c @@ -5,7 +5,7 @@ #include <bootstate.h> #include <fw_config.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c index 97865474..fa4d4d5 100644 --- a/src/mainboard/google/dedede/variants/drawcia/gpio.c +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -7,14 +7,14 @@ #include <fw_config.h> #include <ec/google/chromeec/ec.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config not_board6or8_gpio_table[] = { /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), }; -/* bid6: Pad configuration for board version 6 or 8 in ramstage*/ +/* bid6: Pad configuration for board version 6 or 8 in ramstage */ static const struct pad_config board6or8_gpio_table[] = { /* A10 : WWAN_EN */ diff --git a/src/mainboard/google/dedede/variants/galtic/gpio.c b/src/mainboard/google/dedede/variants/galtic/gpio.c index 79646b5..e2e6669 100644 --- a/src/mainboard/google/dedede/variants/galtic/gpio.c +++ b/src/mainboard/google/dedede/variants/galtic/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A11 : TOUCH_RPT_EN */ diff --git a/src/mainboard/google/dedede/variants/gooey/gpio.c b/src/mainboard/google/dedede/variants/gooey/gpio.c index 123a3bb..5085917 100644 --- a/src/mainboard/google/dedede/variants/gooey/gpio.c +++ b/src/mainboard/google/dedede/variants/gooey/gpio.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/haboki/gpio.c b/src/mainboard/google/dedede/variants/haboki/gpio.c index 03b9a45..12286c6 100644 --- a/src/mainboard/google/dedede/variants/haboki/gpio.c +++ b/src/mainboard/google/dedede/variants/haboki/gpio.c @@ -6,7 +6,7 @@ #include <fw_config.h> #include <ec/google/chromeec/ec.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* C12 : AP_PEN_DET_ODL has an external pull-up and hence no pad termination.*/ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), diff --git a/src/mainboard/google/dedede/variants/kracko/gpio.c b/src/mainboard/google/dedede/variants/kracko/gpio.c index b4c00bd..e8422fd 100644 --- a/src/mainboard/google/dedede/variants/kracko/gpio.c +++ b/src/mainboard/google/dedede/variants/kracko/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/metaknight/gpio.c b/src/mainboard/google/dedede/variants/metaknight/gpio.c index af37d24..072ea7b 100644 --- a/src/mainboard/google/dedede/variants/metaknight/gpio.c +++ b/src/mainboard/google/dedede/variants/metaknight/gpio.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/pirika/gpio.c b/src/mainboard/google/dedede/variants/pirika/gpio.c index 79646b5..e2e6669 100644 --- a/src/mainboard/google/dedede/variants/pirika/gpio.c +++ b/src/mainboard/google/dedede/variants/pirika/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A11 : TOUCH_RPT_EN */ diff --git a/src/mainboard/google/dedede/variants/sasuke/gpio.c b/src/mainboard/google/dedede/variants/sasuke/gpio.c index f101215..8aa9f29 100644 --- a/src/mainboard/google/dedede/variants/sasuke/gpio.c +++ b/src/mainboard/google/dedede/variants/sasuke/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/sasukette/gpio.c b/src/mainboard/google/dedede/variants/sasukette/gpio.c index d9b1307..78d72c7 100644 --- a/src/mainboard/google/dedede/variants/sasukette/gpio.c +++ b/src/mainboard/google/dedede/variants/sasukette/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/storo/gpio.c b/src/mainboard/google/dedede/variants/storo/gpio.c index a73caf5..73b3c2a 100644 --- a/src/mainboard/google/dedede/variants/storo/gpio.c +++ b/src/mainboard/google/dedede/variants/storo/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/waddledee/gpio.c b/src/mainboard/google/dedede/variants/waddledee/gpio.c index 0905e8f..dbb12dc 100644 --- a/src/mainboard/google/dedede/variants/waddledee/gpio.c +++ b/src/mainboard/google/dedede/variants/waddledee/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* E5 : AP_SUB_IO_2 */ PAD_CFG_GPO(GPP_E5, 0, PLTRST), diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index c9b533e..4cdc427 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -8,7 +8,7 @@ #include <gpio.h> #include <soc/gpio.h> -/* GPIO configuration in ramstage*/ +/* GPIO configuration in ramstage */ /* Please make sure that *ALL* GPIOs are configured in this table */ static const struct soc_amd_gpio base_gpio_table[] = { /* PWR_BTN_L */ diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 8a04bd9..d553180 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* SSD1_PWREN CPU SSD1 */ PAD_CFG_GPO(GPP_D14, 1, PLTRST), diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c index 9d17c80..b2e2eec 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /*BT_RF_KILL_N*/ PAD_CFG_GPO(GPP_E11, 1, DEEP), diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index df06865..94a6a79 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST), diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index df06865..94a6a79 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST), diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 82b3931..27395db 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* WWAN_WAKE_N */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index f067af7..b9fdac8 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ PAD_CFG_GPO(GPP_B16, 1, DEEP), diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 889d4e6..1c007d7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ PAD_CFG_GPO(GPP_B16, 1, DEEP), diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c index 91c0417..b6c755a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* Community 0 - GpioGroup GPP_B */ PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Gerrit-Change-Number: 60247 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/dedede/var/beadrix: Enable PIXA touchpad
by Teddy Shih (Code Review) 20 Dec '21

20 Dec '21

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60246 ) Change subject: mb/google/dedede/var/beadrix: Enable PIXA touchpad ...................................................................... mb/google/dedede/var/beadrix: Enable PIXA touchpad This change adds PIXA touchpad into devicetree for beadrix. BUG=b:204882915, b:203113111 TEST=Built and verified touchpad function Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9 --- M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/60246/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 404024b..dab4311 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -37,6 +37,16 @@ }" device domain 0 on - device pci 15.0 on end + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2635"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C 0 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9 Gerrit-Change-Number: 60246 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: starlabs: Convert EC_GPE_SCI to Kconfig
by Paul Menzel (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Sean Rhodes. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60229 ) Change subject: starlabs: Convert EC_GPE_SCI to Kconfig ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189 Gerrit-Change-Number: 60229 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Mon, 20 Dec 2021 06:58:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in vboot[main]: cgpt: Add endian definitions for macOS
by Paul Menzel (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Alex James. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/vboot/+/60235 ) Change subject: cgpt: Add endian definitions for macOS ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/vboot/+/60235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: main Gerrit-Change-Id: I87e98ea157870417f5eba63807eef559e180d1f8 Gerrit-Change-Number: 60235 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alex James <theracermaster(a)gmail.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 06:57:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021