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Change subject: mb/google/dedede/var/bugzzy: Initialize display signals on user mode
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60190/comment/5ae2ce17_98f14039
PS9, Line 14: It takes about 100 ms delay on booting time.
Is it alright to increase the overall boottime? Why can’t the operating system do it?
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Change subject: soc/intel/jsl: Add CdClock config
......................................................................
Patch Set 9:
(2 comments)
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/60009/comment/150a7b5f_58cac252
PS9, Line 409: * CdClock Frequency selection
What does Cd abbreviate?
https://review.coreboot.org/c/coreboot/+/60009/comment/1d5c24d9_9a8eeb37
PS9, Line 411: 0xFF
0xff
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Change subject: mb/google/dedede/var/bugzzy: Initialize display signals on user mode
......................................................................
Patch Set 9:
(5 comments)
File src/mainboard/google/dedede/variants/bugzzy/ramstage.c:
https://review.coreboot.org/c/coreboot/+/60190/comment/6dffa17a_430022cc
PS8, Line 7: #include <drivers/intel/gma/i915_reg.h>
> add one more line, not replace
Done
https://review.coreboot.org/c/coreboot/+/60190/comment/5ad729ba_b8714e62
PS8, Line 9: #define IGD_MMIO_BASE 0xc0010000
> #define IGD_MMIO_BASE(Bus, Dev, Func) (CONFIG_MMCONF_BASE_ADDRESS + (Bus << 20) + (Dev << 15) + (Fun […]
Used 'struct device' and 'pci_read_config32' to get mmio address.
https://review.coreboot.org/c/coreboot/+/60190/comment/f61116c5_c18d5b86
PS8, Line 27: addr32 = IGD_MMIO_BASE;
> addr32 = IGD_MMIO_BASE(0, SA_DEV_SLOT_IGD, 0);
Used 'struct device' and 'pci_read_config32' to get mmio address.
https://review.coreboot.org/c/coreboot/+/60190/comment/a19a730a_94ea9caa
PS8, Line 29: addr32 = IGD_MMIO_BASE + 0x10;
> addr32 = IGD_MMIO_BASE(0, 2, 0) + PCI_BASE_ADDRESS_0;
Used 'struct device' and 'pci_read_config32' to get mmio address.
https://review.coreboot.org/c/coreboot/+/60190/comment/1ef88e24_61149f8f
PS8, Line 36: 0xc7204
> PCH_PP_CONTROL
Done
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Hello build bot (Jenkins), Henry Sun, SH Kim, Simon Yang, Edward Doan, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60190
to look at the new patch set (#9).
Change subject: mb/google/dedede/var/bugzzy: Initialize display signals on user mode
......................................................................
mb/google/dedede/var/bugzzy: Initialize display signals on user mode
Bugzzy uses panel-built-in touch screen, it needs to set panel power
and reset signal to high for touch screen to work.
On user mode, coreboot doesn't initialize graphics since there is no
screen display before OS. So we would add a WA to initialize required
signals on user mode. It takes about 100 ms delay on booting time.
BUG=b:205496327
BRANCH=dedede
TEST=Verified touch screen worked with test coreboot
and test touch screen 028D firmware
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db
---
M src/mainboard/google/dedede/variants/bugzzy/Makefile.inc
A src/mainboard/google/dedede/variants/bugzzy/ramstage.c
2 files changed, 68 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/60190/9
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Change subject: soc/amd/picasso: Add bootloader for recovery
......................................................................
Patch Set 48:
(2 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/57132/comment/38f0ef71_134eb78d
PS48, Line 168: printf("--recovery Enable legacy recovery feature\n");
Mention PSP?
https://review.coreboot.org/c/coreboot/+/57132/comment/0a56e14f_f88bcd21
PS48, Line 1892: satisfie
satisfy
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Change subject: soc/amd/picasso: Add bootloader for recovery
......................................................................
Patch Set 48:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57132/comment/8976b1c8_153c4a33
PS48, Line 9: for AMD's recovery
: mode
Please excuse my ignorance. What is AMD’s recovery mode? Recovery for what? Can you point to some documentation?
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Change subject: mb/google/dedede/var/beadrix: Enable PIXA touchpad
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
You do not need to score your own change-sets.
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Change subject: mb/google/dedede/var/beadrix: Enable audio feature
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/jsl: Add CdClock config
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60009/comment/2a32ba58_effdfbdb
PS7, Line 10:
> 0xff is the default value of CdClock inside of FSP.
Done
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Change subject: mb/google/dedede/var/beadrix: Add internal USB camera support
......................................................................
Patch Set 1: Code-Review+1
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