coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/ironlake: Use `NUM_CHANNELS` macro
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60225 ) Change subject: nb/intel/ironlake: Use `NUM_CHANNELS` macro ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7 Gerrit-Change-Number: 60225 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 20 Dec 2021 09:54:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jsl: Add CdClock config
by Simon Yang (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian. Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jsl: Add CdClock config ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/jasperlake/chip.h: https://review.coreboot.org/c/coreboot/+/60009/comment/995b2b1d_9f63a2cd PS9, Line 411: 0xFF > 0xff Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 11 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 09:52:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: remove root of SoC directory from include path
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60201 ) Change subject: soc/amd: remove root of SoC directory from include path ...................................................................... soc/amd: remove root of SoC directory from include path We shouldn't be providing -I include paths to the root of the soc specific directory. It allows for lazy includes that can collide, but there's no way of knowing the winning path since the winning path is determined by Makefile.inc parsing order. This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff Reviewed-on: https://review.coreboot.org/c/coreboot/+/60201 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7db4719..de16da4 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -54,7 +54,6 @@ smm-y += gpio.c smm-y += smu.c -CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 7d0b86d..16d1eaa 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -66,7 +66,6 @@ smm-y += gpio.c smm-y += psp.c -CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/60201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff Gerrit-Change-Number: 60201 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: use full path of SoC's chip.h
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60202 ) Change subject: mb/google/zork: use full path of SoC's chip.h ...................................................................... mb/google/zork: use full path of SoC's chip.h Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60202 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/shuboz/variant.c M src/mainboard/google/zork/variants/vilboz/variant.c 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 38c5d4a..09d5786 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -7,8 +7,8 @@ #include <boardid.h> #include <ec/google/chromeec/ec.h> #include <FspmUpd.h> +#include <soc/amd/picasso/chip.h> #include <soc/platform_descriptors.h> -#include "chip.h" const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); /* diff --git a/src/mainboard/google/zork/variants/shuboz/variant.c b/src/mainboard/google/zork/variants/shuboz/variant.c index 9907c72..b0a6b7e 100644 --- a/src/mainboard/google/zork/variants/shuboz/variant.c +++ b/src/mainboard/google/zork/variants/shuboz/variant.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <soc/amd/picasso/chip.h> #include <soc/pci_devs.h> -#include "chip.h" uint32_t usb_oc_map_override[USB_PORT_COUNT] = { USB_OC_PIN_0, diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 43ca0e5..ddfce69 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -4,7 +4,7 @@ #include <soc/pci_devs.h> #include <fw_config.h> #include <sar.h> -#include "chip.h" +#include <soc/amd/picasso/chip.h> static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { { // DDI0, DP0, eDP -- To view, visit https://review.coreboot.org/c/coreboot/+/60202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd Gerrit-Change-Number: 60202 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/bilby,mandolin: use full path of SoC's chip.h
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60200 ) Change subject: mb/amd/bilby,mandolin: use full path of SoC's chip.h ...................................................................... mb/amd/bilby,mandolin: use full path of SoC's chip.h This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60200 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/mandolin/mainboard.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index bc91630..c41e1b7 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -12,7 +12,7 @@ #include <soc/platform_descriptors.h> #include <types.h> #include <commonlib/helpers.h> -#include <chip.h> +#include <soc/amd/picasso/chip.h> #include "gpio.h" #include "mainboard.h" diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index a66db78..06edaa0 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -10,7 +10,7 @@ #include <soc/pci_devs.h> #include <types.h> #include <commonlib/helpers.h> -#include <chip.h> +#include <soc/amd/picasso/chip.h> #include "gpio.h" /* TODO: recheck IRQ tables */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 Gerrit-Change-Number: 60200 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/stoneyridge/include/southbridge: remove unneeded chip.h include
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60199 ) Change subject: soc/amd/stoneyridge/include/southbridge: remove unneeded chip.h include ...................................................................... soc/amd/stoneyridge/include/southbridge: remove unneeded chip.h include Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9b37efc89e505c2de99536b59e7d7e2bb1d54bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/60199 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 2773751..e00bf8e 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -7,7 +7,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <soc/iomap.h> -#include "chip.h" /* * AcpiMmio Region -- To view, visit https://review.coreboot.org/c/coreboot/+/60199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b37efc89e505c2de99536b59e7d7e2bb1d54bff Gerrit-Change-Number: 60199 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.h
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60198 ) Change subject: mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.h ...................................................................... mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.h This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I10a18efb92ac0c3cad31044156e32aa6afe1d4d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60198 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/gardenia/OemCustomize.c M src/mainboard/amd/padmelon/OemCustomize.c M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c 4 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 210a05b..d86313f 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include <amdblocks/agesawrapper.h> #define DIMMS_PER_CHANNEL 2 diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c index 7ea46f8..e65f750 100644 --- a/src/mainboard/amd/padmelon/OemCustomize.c +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include <amdblocks/agesawrapper.h> #define DIMMS_PER_CHANNEL 1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 349fe34..9f37a46 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include <amdblocks/agesawrapper.h> #include <gpio.h> #include <console/console.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 79fd478..a3dfa15 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -2,7 +2,7 @@ #include <amdblocks/agesawrapper.h> #include <variant/gpio.h> -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include <soc/pci_devs.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/60198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a18efb92ac0c3cad31044156e32aa6afe1d4d1 Gerrit-Change-Number: 60198 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jsl: Add CdClock config
by Simon Yang (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Jamie Chen, Henry Sun, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60009 to look at the new patch set (#11). Change subject: soc/intel/jsl: Add CdClock config ...................................................................... soc/intel/jsl: Add CdClock config This dev tree config controls the CdClock for Jasper Lake. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 11 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includes
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60197 ) Change subject: mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includes ...................................................................... mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includes Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie716633bd7602d5e4a7e186aa9e444b7f70dab56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60197 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/gardenia/bootblock/bootblock.c M src/mainboard/amd/gardenia/gpio.h M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/padmelon/bootblock/bootblock.c M src/mainboard/amd/padmelon/gpio.c M src/mainboard/amd/padmelon/mainboard.c M src/mainboard/google/kahlee/mainboard.c 7 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c index a480f36..0543c31 100644 --- a/src/mainboard/amd/gardenia/bootblock/bootblock.c +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/gpio.h> #include <soc/southbridge.h> #include "../gpio.h" diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h index 3e9500d..d01bdfd 100644 --- a/src/mainboard/amd/gardenia/gpio.h +++ b/src/mainboard/amd/gardenia/gpio.h @@ -3,6 +3,8 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H +#include <soc/gpio.h> + const struct soc_amd_gpio *early_gpio_table(size_t *size); const struct soc_amd_gpio *gpio_table(size_t *size); diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index ae72b33..459aeba 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> +#include <soc/gpio.h> #include <soc/southbridge.h> #include "gpio.h" diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c index c93ef52..f1b6822 100644 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -4,6 +4,7 @@ #include <soc/southbridge.h> #include <amdblocks/lpc.h> #include <device/pci_ops.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> #include <drivers/uart/uart8250reg.h> #include <arch/io.h> diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index 9c18d30..0de2c0a 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -2,6 +2,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> +#include <soc/gpio.h> #include <soc/southbridge.h> #include "gpio.h" diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c index 51b0f90..017a1fb 100644 --- a/src/mainboard/amd/padmelon/mainboard.c +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -5,6 +5,7 @@ #include <acpi/acpi.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ffec6a5..e54ac74 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -11,6 +11,7 @@ #include <baseboard/variants.h> #include <boardid.h> #include <smbios.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie716633bd7602d5e4a7e186aa9e444b7f70dab56 Gerrit-Change-Number: 60197 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jsl: Add CdClock config
by Simon Yang (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Simon Yang, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Jamie Chen, Henry Sun, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60009 to look at the new patch set (#10). Change subject: soc/intel/jsl: Add CdClock config ...................................................................... soc/intel/jsl: Add CdClock config This dev tree config controls the CdClock for Jasper Lake. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021