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Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
......................................................................
Patch Set 4:
(2 comments)
File src/cpu/x86/smm/smm_stub.S:
https://review.coreboot.org/c/coreboot/+/58386/comment/42c121ca_3f4fd2df
PS4, Line 108: jc 1f
I always confuse these conditionals, jumps if eax < 0xb ?
https://review.coreboot.org/c/coreboot/+/58386/comment/a8b2676e_9a819c3f
PS4, Line 124: cmp (%ebx, %ecx, 2), %ax
Does it make sense to optimise the table to 16bits of LAPIC ID?
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Change subject: cpu/x86/lapic: Support switching to X2APIC mode
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
CB:60213 suggests some work-around or solution for X2APIC_ONLY choice.
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Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS2:
> Kyösti wrote on the IRC channel: "hell had some failure with x2apic mode, not sure if this was relat […]
This was not related to X2APIC_ONLY choice problem.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60213
to look at the new patch set (#2).
Change subject: [WIP] cpu/x86/lapic: Fix choice X2APIC_ONLY
......................................................................
[WIP] cpu/x86/lapic: Fix choice X2APIC_ONLY
When sending self an IPI, some instructions may be processed
before IPI is serviced. Spend some time doing nothing, to
avoid entering a printk() and acquiring console_lock and
dead-locking.
Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/x86/mp_init.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/60213/2
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Hello build bot (Jenkins), Wonkyu Kim, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55262
to look at the new patch set (#14).
Change subject: cpu/x86/lapic: Support switching to X2APIC mode
......................................................................
cpu/x86/lapic: Support switching to X2APIC mode
The options X2APIC_ONLY and X2APIC_RUNTIME were already user-visible
choices in menuconfig, but the functionality was not actually provided
except for platforms where FSP presumably enabled X2APIC.
Add the logic and related logging for switching to X2APIC operation.
TEST: qemu-system-x86_64 -M Q35 -accel kvm -bios coreboot.rom -serial
stdio -smp 2
PARALLEL_MP, and either X2APIC_ONLY or X2APIC_RUNTIME, need to be
selected for the build of emulation/qemu-q35.
Change-Id: I19a990ba287d21ccddaa64601923f1c4830e95e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/x86/lapic/lapic.c
M src/cpu/x86/mp_init.c
M src/include/cpu/x86/lapic.h
M src/include/cpu/x86/msr.h
4 files changed, 39 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/55262/14
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Hello build bot (Jenkins), Angel Pons, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58386
to look at the new patch set (#4).
Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
......................................................................
cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
Even when we're not in X2APIC mode, the information in CPUID
leaf 0xb will be valid if that leaf is implemented on the CPU.
Change-Id: I0f1f46fe5091ebeab6dfb4c7e151150cf495d0cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/x86/smm/smm_stub.S
M src/include/cpu/x86/lapic.h
2 files changed, 8 insertions(+), 13 deletions(-)
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Change subject: soc/intel/jsl: Add CdClock config
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/60009/comment/0c43680e_6450aa5c
PS9, Line 409: * CdClock Frequency selection
> "Core Display" clock
Do you mean I need to change it to "Core Display Clock Frequency selection"?
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Change subject: soc/intel/jsl: Add CdClock config
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/60009/comment/a20b30dd_3615bc3f
PS9, Line 409: * CdClock Frequency selection
> What does Cd abbreviate?
"Core Display" clock
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Change subject: mb/google/dedede/var/bugzzy: Initialize display signals on user mode
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/dedede/variants/bugzzy/ramstage.c:
https://review.coreboot.org/c/coreboot/+/60190/comment/0d3a84a0_166d9022
PS9, Line 64: mdelay(60);
maybe try to remove this delay to speed up post time? or record timestamp by "timestamp_add_now" and ensure there still have enough time(>60ms) before boot into kernel.
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