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Change subject: mb/starlabs/labtop: Update VBT
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Patch Set 11: Code-Review+2
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Change subject: mb/google/guybrush/var/nipperkin: update telemetry settings
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60243/comment/712ae039_b9d86268
PS2, Line 15:
> Ack. Done and for the 2nd query, as the message described: […]
Done
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Change subject: mb/google/guybrush/var/nipperkin: update telemetry settings
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60243/comment/78401a06_48ce31b6
PS2, Line 9: update
> Update
Done
https://review.coreboot.org/c/coreboot/+/60243/comment/c1ec5ba3_3a90f211
PS2, Line 15:
> … and what performance was improved how.
Ack. Done and for the 2nd query, as the message described:
"2. pass AMD SDLE/Stardust test"
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Hello build bot (Jenkins), Martin Roth, Bhanu Prakash Maiya, Eric Peers, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/guybrush/var/nipperkin: update telemetry settings
......................................................................
mb/google/guybrush/var/nipperkin: update telemetry settings
Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
vdd scale: 73457 -> 73331
vdd offset: 291 -> 1893
soc scale: 30761 -> 31955
soc offset: 834 -> 852
BUG=b:207299255
BRANCH=guybrush
TEST=1. emerge-guybrush coreboot
2. pass AMD SDLE/Stardust test
Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6
Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
---
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/60243/3
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Change subject: mb/starlabs/labtop: Update VBT
......................................................................
Patch Set 11:
(1 comment)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/59727/comment/94891055_22594769
PS9, Line 7: Vbt
> nit: VBT
Done
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Change subject: mb/starlabs/labtop: Store serial number in CMOS
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> Well, I have some ideas. Depending on your manufacturing process one of these might work. If you would like to discuss that in a private chat, feel free to ping me on IRC. I am flx there.
I'd be interested in joining the discussion. I wouldn't want to go over what has already been discussed when reviewing the implementation.
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Change subject: mb/starlabs/labtop: Store serial number in CMOS
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> nvramtool
Well, I have some ideas. Depending on your manufacturing process one of these might work. If you would like to discuss that in a private chat, feel free to ping me on IRC. I am flx there.
However, I didn't want to create a blocker. From my perspective, it is up to you how you want to do it.
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Change subject: soc/amd/*: PSP verstage minbuild
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59585/comment/436cfda3_43cfeb00
PS2, Line 9: The PSP that is supplied for Picasso AMD-based chromebooks currently
: requires a psp_verstage to boot
> i have a non-chromebook picasso apu on my mandolin board and it doesn't require (or support) verstag […]
If generic PSP images exist, it would be nice to just put something without
verstage requirement into `3rdparty/amd_blobs`. Or is it there already? IOW,
is what we have in the blobs repo what ships with these Chromebooks?
Or is it preferred to keep the original PSP firmware when flashing a stock
coreboot w/o vboot?
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Change subject: mb/starlabs/labtop: Store serial number in CMOS
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> > Can't see how we program the serial number on a per-board basis in production. […]
nvramtool
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