coreboot-gerrit December 2021

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/60257 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/60257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c571f3 Gerrit-Change-Number: 60257 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Tim Wawrzynczak. Saurabh Mishra has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/60257 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/60257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c571f3 Gerrit-Change-Number: 60257 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60257 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Updated LpmStateEnableMask UPD change-Id: I0c6ae72610da39fc18ff252c440d006e83c571f3 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/alderlake/meminit.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/60257/1 diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index bdc4450..52a816f 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -189,7 +189,7 @@ &mem_cfg->DqMapCpu2DramMc1Ch3, }; - const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!"); @@ -210,7 +210,7 @@ &mem_cfg->DqsMapCpu2DramMc1Ch3, }; - const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!"); -- To view, visit https://review.coreboot.org/c/coreboot/+/60257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c571f3 Gerrit-Change-Number: 60257 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/60256 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/60256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c573f3 Gerrit-Change-Number: 60256 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Tim Wawrzynczak. Saurabh Mishra has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/60256 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/60256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c573f3 Gerrit-Change-Number: 60256 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60192 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c543b2 Gerrit-Change-Number: 60192 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60256 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Updated LpmStateEnableMask UPD change-Id: I0c6ae72610da39fc18ff252c440d006e83c573f3 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/meminit.c 2 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/60256/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 251b252..b1463fc 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -642,7 +642,7 @@ for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); - s_cfg->LpmStateEnableMask = get_supported_lpm_mask(); + s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); /* Apply minimum assertion width settings */ if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 44071db..bdc4450 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -123,14 +123,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { - [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, - [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, - [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, - [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, - [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, - [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, - [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, - [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, + [2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, }, + [3] = { &mem_cfg->MemorySpdPtr030, &mem_cfg->MemorySpdPtr031, }, + [4] = { &mem_cfg->MemorySpdPtr100, &mem_cfg->MemorySpdPtr101, }, + [5] = { &mem_cfg->MemorySpdPtr110, &mem_cfg->MemorySpdPtr111, }, + [6] = { &mem_cfg->MemorySpdPtr120, &mem_cfg->MemorySpdPtr121, }, + [7] = { &mem_cfg->MemorySpdPtr130, &mem_cfg->MemorySpdPtr131, }, }; uint8_t *disable_channel_upds[MRC_CHANNELS] = { &mem_cfg->DisableMc0Ch0, @@ -179,14 +179,14 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dq_upds[MRC_CHANNELS] = { - &mem_cfg->DqMapCpu2DramCh0, - &mem_cfg->DqMapCpu2DramCh1, - &mem_cfg->DqMapCpu2DramCh2, - &mem_cfg->DqMapCpu2DramCh3, - &mem_cfg->DqMapCpu2DramCh4, - &mem_cfg->DqMapCpu2DramCh5, - &mem_cfg->DqMapCpu2DramCh6, - &mem_cfg->DqMapCpu2DramCh7, + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch1, + &mem_cfg->DqMapCpu2DramMc0Ch2, + &mem_cfg->DqMapCpu2DramMc0Ch3, + &mem_cfg->DqMapCpu2DramMc1Ch0, + &mem_cfg->DqMapCpu2DramMc1Ch1, + &mem_cfg->DqMapCpu2DramMc1Ch2, + &mem_cfg->DqMapCpu2DramMc1Ch3, }; const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0); @@ -200,14 +200,14 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dqs_upds[MRC_CHANNELS] = { - &mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1, - &mem_cfg->DqsMapCpu2DramCh2, - &mem_cfg->DqsMapCpu2DramCh3, - &mem_cfg->DqsMapCpu2DramCh4, - &mem_cfg->DqsMapCpu2DramCh5, - &mem_cfg->DqsMapCpu2DramCh6, - &mem_cfg->DqsMapCpu2DramCh7, + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch1, + &mem_cfg->DqsMapCpu2DramMc0Ch2, + &mem_cfg->DqsMapCpu2DramMc0Ch3, + &mem_cfg->DqsMapCpu2DramMc1Ch0, + &mem_cfg->DqsMapCpu2DramMc1Ch1, + &mem_cfg->DqsMapCpu2DramMc1Ch2, + &mem_cfg->DqsMapCpu2DramMc1Ch3, }; const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0); -- To view, visit https://review.coreboot.org/c/coreboot/+/60256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c573f3 Gerrit-Change-Number: 60256 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*: PSP verstage minbuild
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Jason Glenesk, Nico Huber, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59585 ) Change subject: soc/amd/*: PSP verstage minbuild ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59585/comment/865b07e9_0bb6148d PS2, Line 9: The PSP that is supplied for Picasso AMD-based chromebooks currently : requires a psp_verstage to boot > If generic PSP images exist, it would be nice to just put something without […] the same PSP firmware from the amd_blobs repository can be used on chromebook and non-chromebook silicon. only when it runs on chromebook silicon, it'll run verstage on the PSP. using the PSP firmware from a UEFI-based firmware probably won't work with coreboot+FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/59585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie506193d21207ecabe65158e84dc02eec1cf5b26 Gerrit-Change-Number: 59585 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 12:24:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Update VBT
by Andy Pont (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Sean Rhodes, Paul Menzel. Andy Pont has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59727 ) Change subject: mb/starlabs/labtop: Update VBT ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec Gerrit-Change-Number: 59727 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 20 Dec 2021 12:19:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add enum for `power_profile`
by Angel Pons (Code Review) 20 Dec '21

20 Dec '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60212 ) Change subject: mb/starlabs/labtop: Add enum for `power_profile` ...................................................................... mb/starlabs/labtop: Add enum for `power_profile` Introduce and use an enum for the `power_profile` CMOS option. Add a helper function that converts CMOS values into enum values. Using an enum allows GCC to warn about switch statements using enum types for their control expressions not handling all possible enum values, and also improves readability. Change-Id: I47a453ea12d164d26908a9944a89a481757e753c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60212 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <admin(a)starlabs.systems> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/starlabs/labtop/include/variants.h M src/mainboard/starlabs/labtop/mainboard.c M src/mainboard/starlabs/labtop/variants/tgl/devtree.c 3 files changed, 29 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Sean Rhodes: Looks good to me, but someone else must approve diff --git a/src/mainboard/starlabs/labtop/include/variants.h b/src/mainboard/starlabs/labtop/include/variants.h index c95d15b..0dd41c0 100644 --- a/src/mainboard/starlabs/labtop/include/variants.h +++ b/src/mainboard/starlabs/labtop/include/variants.h @@ -5,6 +5,15 @@ #include <soc/gpio.h> +enum cmos_power_profile { + PP_POWER_SAVER = 0, + PP_BALANCED = 1, + PP_PERFORMANCE = 2, +}; +#define NUM_POWER_PROFILES 3 + +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback); + /* * The next set of functions return the gpio table and fill in the number of * entries for each table. diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c index 60e65ee..d394f25 100644 --- a/src/mainboard/starlabs/labtop/mainboard.c +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -5,6 +5,12 @@ #include <option.h> #include <variants.h> +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback) +{ + const unsigned int power_profile = get_uint_option("power_profile", fallback); + return power_profile < NUM_POWER_PROFILES ? power_profile : fallback; +} + static void init_mainboard(void *chip_info) { const struct pad_config *pads; diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c index 42a5aff..09d26e8 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c @@ -24,26 +24,26 @@ /* Update PL1 & PL2 based on CMOS settings */ - switch (get_uint_option("power_profile", 0)) { - case 1: - soc_conf_2core->tdp_pl1_override = 15; - soc_conf_4core->tdp_pl1_override = 15; - soc_conf_2core->tdp_pl2_override = 25; - soc_conf_4core->tdp_pl2_override = 25; - break; - case 2: - soc_conf_2core->tdp_pl1_override = 28; - soc_conf_4core->tdp_pl1_override = 28; - soc_conf_2core->tdp_pl2_override = 40; - soc_conf_4core->tdp_pl2_override = 40; - break; - default: + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: disable_turbo(); soc_conf_2core->tdp_pl1_override = 15; soc_conf_4core->tdp_pl1_override = 15; soc_conf_2core->tdp_pl2_override = 15; soc_conf_4core->tdp_pl2_override = 15; break; + case PP_BALANCED: + soc_conf_2core->tdp_pl1_override = 15; + soc_conf_4core->tdp_pl1_override = 15; + soc_conf_2core->tdp_pl2_override = 25; + soc_conf_4core->tdp_pl2_override = 25; + break; + case PP_PERFORMANCE: + soc_conf_2core->tdp_pl1_override = 28; + soc_conf_4core->tdp_pl1_override = 28; + soc_conf_2core->tdp_pl2_override = 40; + soc_conf_4core->tdp_pl2_override = 40; + break; } /* Enable/Disable Wireless based on CMOS settings */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a453ea12d164d26908a9944a89a481757e753c Gerrit-Change-Number: 60212 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021