coreboot-gerrit December 2021

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60258 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c574f3 Gerrit-Change-Number: 60258 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60259 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Updated LpmStateEnableMask UPD change-Id: I0c6ae72610da39fc18ff252c440d006e83c576f3 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/meminit.c 2 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/60259/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 251b252..b1463fc 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -642,7 +642,7 @@ for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); - s_cfg->LpmStateEnableMask = get_supported_lpm_mask(); + s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); /* Apply minimum assertion width settings */ if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 44071db..52a816f 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -123,14 +123,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { - [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, - [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, - [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, - [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, - [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, - [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, - [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, - [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, + [2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, }, + [3] = { &mem_cfg->MemorySpdPtr030, &mem_cfg->MemorySpdPtr031, }, + [4] = { &mem_cfg->MemorySpdPtr100, &mem_cfg->MemorySpdPtr101, }, + [5] = { &mem_cfg->MemorySpdPtr110, &mem_cfg->MemorySpdPtr111, }, + [6] = { &mem_cfg->MemorySpdPtr120, &mem_cfg->MemorySpdPtr121, }, + [7] = { &mem_cfg->MemorySpdPtr130, &mem_cfg->MemorySpdPtr131, }, }; uint8_t *disable_channel_upds[MRC_CHANNELS] = { &mem_cfg->DisableMc0Ch0, @@ -179,17 +179,17 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dq_upds[MRC_CHANNELS] = { - &mem_cfg->DqMapCpu2DramCh0, - &mem_cfg->DqMapCpu2DramCh1, - &mem_cfg->DqMapCpu2DramCh2, - &mem_cfg->DqMapCpu2DramCh3, - &mem_cfg->DqMapCpu2DramCh4, - &mem_cfg->DqMapCpu2DramCh5, - &mem_cfg->DqMapCpu2DramCh6, - &mem_cfg->DqMapCpu2DramCh7, + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch1, + &mem_cfg->DqMapCpu2DramMc0Ch2, + &mem_cfg->DqMapCpu2DramMc0Ch3, + &mem_cfg->DqMapCpu2DramMc1Ch0, + &mem_cfg->DqMapCpu2DramMc1Ch1, + &mem_cfg->DqMapCpu2DramMc1Ch2, + &mem_cfg->DqMapCpu2DramMc1Ch3, }; - const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!"); @@ -200,17 +200,17 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dqs_upds[MRC_CHANNELS] = { - &mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1, - &mem_cfg->DqsMapCpu2DramCh2, - &mem_cfg->DqsMapCpu2DramCh3, - &mem_cfg->DqsMapCpu2DramCh4, - &mem_cfg->DqsMapCpu2DramCh5, - &mem_cfg->DqsMapCpu2DramCh6, - &mem_cfg->DqsMapCpu2DramCh7, + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch1, + &mem_cfg->DqsMapCpu2DramMc0Ch2, + &mem_cfg->DqsMapCpu2DramMc0Ch3, + &mem_cfg->DqsMapCpu2DramMc1Ch0, + &mem_cfg->DqsMapCpu2DramMc1Ch1, + &mem_cfg->DqsMapCpu2DramMc1Ch2, + &mem_cfg->DqsMapCpu2DramMc1Ch3, }; - const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!"); -- To view, visit https://review.coreboot.org/c/coreboot/+/60259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c576f3 Gerrit-Change-Number: 60259 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/starlabs: Add LabTop Mk IV
by Angel Pons (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mainboard/starlabs: Add LabTop Mk IV ...................................................................... Patch Set 71: (1 comment) File src/mainboard/starlabs/labtop/variants/cml/devicetree.cb: https://review.coreboot.org/c/coreboot/+/58428/comment/2c1a8fcd_9c1dd75e PS66, Line 125: device pci 19.0 off end # I2C4 > Would the same apply to TGL? Haven't checked, but I think so. -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 71 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Mon, 20 Dec 2021 13:11:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: starlabs: Convert EC_GPE_SCI to Kconfig
by Angel Pons (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60229 ) Change subject: starlabs: Convert EC_GPE_SCI to Kconfig ...................................................................... Patch Set 3: Code-Review+1 (4 comments) Patchset: PS3: Thanks! File src/ec/starlabs/merlin/Kconfig: https://review.coreboot.org/c/coreboot/+/60229/comment/8626fdbf_376724b1 PS3, Line 59: GPI GP*E* If this somehow clashes with macro names, I'd just add a `STARLABS_` prefix or something. File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/60229/comment/50098d06_f01fb620 PS3, Line 54: GPI GP*E* File src/mainboard/starlabs/labtop/dsdt.asl: https://review.coreboot.org/c/coreboot/+/60229/comment/37337586_cbb292ba PS3, Line 3: #define EC_GPE_SCI CONFIG_EC_GPE_SCI Please also drop the define. It's currently only used in one place in your EC code: src/ec/starlabs/merlin/acpi/ec.asl: Name (_GPE, EC_GPE_SCI) -- To view, visit https://review.coreboot.org/c/coreboot/+/60229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189 Gerrit-Change-Number: 60229 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Mon, 20 Dec 2021 13:11:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] smp/spinlock: Use compiler builtins
by Angel Pons (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Raul Rangel, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60253 ) Change subject: [RFC] smp/spinlock: Use compiler builtins ...................................................................... Patch Set 1: (1 comment) File src/include/rules.h: https://review.coreboot.org/c/coreboot/+/60253/comment/a235a200_af186beb PS1, Line 306: /* TODO: Enable in all x86 stages */ comment seems outdated -- To view, visit https://review.coreboot.org/c/coreboot/+/60253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6694784aa0810cd877886ef95434f62e3aefce6c Gerrit-Change-Number: 60253 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 13:08:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/60258 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/60258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c574f3 Gerrit-Change-Number: 60258 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Tim Wawrzynczak. Saurabh Mishra has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/60258 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/60258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c574f3 Gerrit-Change-Number: 60258 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60256 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c573f3 Gerrit-Change-Number: 60256 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60258 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Updated LpmStateEnableMask UPD change-Id: I0c6ae72610da39fc18ff252c440d006e83c574f3 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/meminit.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/60258/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index b1463fc..64bb1ff 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/*SPDX-License-Identifier: GPL-2.0-only*/ #include <assert.h> #include <cbfs.h> diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 52a816f..fe1eb21 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*SPDX-License-Identifier: GPL-2.0-or-later*/ #include <console/console.h> #include <fsp/util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c574f3 Gerrit-Change-Number: 60258 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 20 Dec '21

20 Dec '21

Saurabh Mishra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60257 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c571f3 Gerrit-Change-Number: 60257 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: abandon

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coreboot-gerrit December 2021