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Hello build bot (Jenkins), Jamie Chen, Henry Sun, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60009
to look at the new patch set (#14).
Change subject: soc/intel/jsl: Add CdClock config
......................................................................
soc/intel/jsl: Add CdClock config
This dev tree config controls the CdClock for Jasper Lake.
BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
3 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/14
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Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )
Change subject: soc/intel/jsl: Add CdClock config
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/60009/comment/446a7c04_e61e7220
PS9, Line 409: * CdClock Frequency selection
> It would help me, and doesn’t hurt in my opinion.
Done
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Hello build bot (Jenkins), Jamie Chen, Henry Sun, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60009
to look at the new patch set (#13).
Change subject: soc/intel/jsl: Add CdClock config
......................................................................
soc/intel/jsl: Add CdClock config
This dev tree config controls the CdClock for Jasper Lake.
BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
3 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/13
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Attention is currently required from: Jamie Chen, Henry Sun, Simon Yang, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian.
Hello build bot (Jenkins), Jamie Chen, Henry Sun, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60009
to look at the new patch set (#12).
Change subject: soc/intel/jsl: Add CdClock config
......................................................................
soc/intel/jsl: Add CdClock config
This dev tree config controls the CdClock for Jasper Lake.
BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
---
A play Clock Frequency selectionq:q!
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
4 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/12
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Change subject: mb/starlabs/labtop: Store serial number in CMOS
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> Can't see how we program the serial number on a per-board basis in production.
How would you do that with CMOS?
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Change subject: soc/intel/jsl: Add CdClock config
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/60009/comment/b95ddd48_ecd4e626
PS9, Line 409: * CdClock Frequency selection
> Do you mean I need to change it to "Core Display Clock Frequency selection"?
It would help me, and doesn’t hurt in my opinion.
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Change subject: mb/starlabs/labtop: Store serial number in CMOS
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> I haven't used it, but it makes much more sense.
Makes sense and I can see what needs enabling in the build to make it work. Can't see how we program the serial number on a per-board basis in production.
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