coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Configure GPIO settings
by Teddy Shih (Code Review) 20 Dec '21

20 Dec '21

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60245 ) Change subject: mb/google/dedede/var/beadrix: Configure GPIO settings ...................................................................... mb/google/dedede/var/beadrix: Configure GPIO settings Override GPIO pad configurations based on the beadrix's schematic. BUG=b:204882915 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I53fc8088ff8ebb2790ac8cd68186cf9de908b414 --- M src/mainboard/google/dedede/variants/beadrix/Makefile.inc A src/mainboard/google/dedede/variants/beadrix/gpio.c 2 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/60245/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/Makefile.inc index 566f5cc..e835c69 100644 --- a/src/mainboard/google/dedede/variants/beadrix/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/Makefile.inc @@ -1,3 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/beadrix/gpio.c b/src/mainboard/google/dedede/variants/beadrix/gpio.c new file mode 100644 index 0000000..368818d --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/gpio.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A11 : TOUCH_RPT_EN ==> NC */ + PAD_NC(GPP_A11, NONE), + + /* C18 : AP_I2C_EMR_SDA ==> NC */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL ==> NC */ + PAD_NC(GPP_C19, NONE), + /* C22 : UART2_RTS_N ==> NC */ + PAD_NC(GPP_C22, NONE), + + /* D12 : WCAM_RST_L ==> NC */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : EN_PP1200_CAMERA ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 ==> TP */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 ==> TP */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 ==> TP */ + PAD_NC(GPP_D21, NONE), + + /* E1 : EMR_RESET_L ==> NC */ + PAD_NC(GPP_E1, NONE), + /* E2 : CLK_24M_WCAM ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E5 : AP_SUB_IO_2 ==> TP */ + PAD_NC(GPP_E5, NONE), + /* E10 : GPP_E10/SML_DATA0 ==> NC */ + PAD_NC(GPP_E10, NONE), + + /* G0 : SD_CMD ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK ==> NC */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP ==> NC */ + PAD_NC(GPP_G7, NONE), + + /* H1 : EN_PP3300_SD_U ==> NC */ + PAD_NC(GPP_H1, NONE), +}; + +/* TODO static const struct pad_config lte_disable_pads[] = { + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_H17, NONE), +}; */ + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* TODO static void fw_config_handle(void *unused) +{ + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_1A_LTE))) + gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53fc8088ff8ebb2790ac8cd68186cf9de908b414 Gerrit-Change-Number: 60245 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Correct memory settings
by Teddy Shih (Code Review) 20 Dec '21

20 Dec '21

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60244 ) Change subject: mb/google/dedede/var/beadrix: Correct memory settings ...................................................................... mb/google/dedede/var/beadrix: Correct memory settings Based on the beadrix's schematic, generate memory settings. BUG=b:204882915, b:210123929 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I935581fbf21be4820b03a608ea5bd60b1c000baa --- A src/mainboard/google/dedede/variants/beadrix/Makefile.inc A src/mainboard/google/dedede/variants/beadrix/memory.c 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/60244/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/Makefile.inc new file mode 100644 index 0000000..566f5cc --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +romstage-y += memory.c diff --git a/src/mainboard/google/dedede/variants/beadrix/memory.c b/src/mainboard/google/dedede/variants/beadrix/memory.c new file mode 100644 index 0000000..bfef45b --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static const struct mb_cfg board_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x00, 0x0}, + {0x00, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on SoC + * the value = pin number on LPDDR4 part + */ + .dqs_map[DDR_CH0] = {0, 3, 2, 1, 7, 5, 4, 6}, + .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 7, 6, 5}, + + /* Disable Early Command Training */ + .ect = 1, + + /* User Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &board_memcfg_cfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I935581fbf21be4820b03a608ea5bd60b1c000baa Gerrit-Change-Number: 60244 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update telemetry settings
by Kevin Chiu (Code Review) 20 Dec '21

20 Dec '21

Kevin Chiu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/60243 ) Change subject: mb/google/guybrush/var/nipperkin: update telemetry settings ...................................................................... mb/google/guybrush/var/nipperkin: update telemetry settings update telemetry to improve the performance. vdd scale: 73457 -> 73331 vdd offset: 291 -> 1893 soc scale: 30761 -> 31955 soc offset: 834 -> 852 BUG=b:207299255 BRANCH=guybrush TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE/Stardust test Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/60243/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Gerrit-Change-Number: 60243 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update telemetry settings
by Kevin Chiu (Code Review) 20 Dec '21

20 Dec '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60243 ) Change subject: mb/google/guybrush/var/nipperkin: update telemetry settings ...................................................................... mb/google/guybrush/var/nipperkin: update telemetry settings update telemetry to improve the performance. vdd scale: 73457 -> 73331 vdd offset: 291 -> 1893 soc scale: 30761 -> 31955 soc offset: 834 -> 852 BUG=b:207299255 BRANCH=guybrush TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE/Stardust test Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/60243/1 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 19c6fe1..c7917ae 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -61,10 +61,10 @@ register "sustained_power_limit_mW" = "15000" register "thermctl_limit_degreeC" = "100" - register "telemetry_vddcrvddfull_scale_current_mA" = "73457" #mA - register "telemetry_vddcrvddoffset" = "291" - register "telemetry_vddcrsocfull_scale_current_mA" = "30761" #mA - register "telemetry_vddcrsocoffset" = "834" + register "telemetry_vddcrvddfull_scale_current_mA" = "73331" #mA + register "telemetry_vddcrvddoffset" = "1893" + register "telemetry_vddcrsocfull_scale_current_mA" = "31955" #mA + register "telemetry_vddcrsocoffset" = "852" # I2C Config #+-------------------+---------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/60243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Gerrit-Change-Number: 60243 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Add memory part and generate DRAM ID
by Teddy Shih (Code Review) 20 Dec '21

20 Dec '21

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60242 ) Change subject: mb/google/dedede/var/beadrix: Add memory part and generate DRAM ID ...................................................................... mb/google/dedede/var/beadrix: Add memory part and generate DRAM ID This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:204882915, b:210123929 BRANCH=None TEST=Run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: Ibff150bb4e742f32641da661cfca6594d18c52e9 --- M src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc M src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/60242/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc index 6751a42..d513880 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt index fa24790..3af2e18 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -1 +1,3 @@ DRAM Part Name ID to assign +MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt index 9621137..ba69c43 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -1,11 +1,2 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name +MT53E512M32D1NP-046 WT:B +K4U6E3S4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/60242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibff150bb4e742f32641da661cfca6594d18c52e9 Gerrit-Change-Number: 60242 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by Maulik V Vaghela (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Anilkumar N, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Usha P. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59937 ) Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/adlrvp/early_gpio_n.c: https://review.coreboot.org/c/coreboot/+/59937/comment/0e98941b_e2b6c2af PS7, Line 19: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1), Do we really need to configure CPU PCIe vGPIO considering number of CPU root port are 0? https://review.coreboot.org/c/coreboot/+/59752/10/src/soc/intel/alderlake/K… -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 7 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 06:18:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Correct memory settings
by Teddy Shih (Code Review) 20 Dec '21

20 Dec '21

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60241 ) Change subject: mb/google/dedede/var/beadrix: Correct memory settings ...................................................................... mb/google/dedede/var/beadrix: Correct memory settings Based on the beadrix's schematic, generate memory settings. BUG=b:204882915, b:210123929 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I0f01ad05dbff122534f1997e3f72e83b9333ffc0 --- A src/mainboard/google/dedede/variants/beadrix/Makefile.inc A src/mainboard/google/dedede/variants/beadrix/memory.c 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60241/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/Makefile.inc new file mode 100644 index 0000000..566f5cc --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +romstage-y += memory.c diff --git a/src/mainboard/google/dedede/variants/beadrix/memory.c b/src/mainboard/google/dedede/variants/beadrix/memory.c new file mode 100644 index 0000000..bfef45b --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static const struct mb_cfg board_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x00, 0x0}, + {0x00, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on SoC + * the value = pin number on LPDDR4 part + */ + .dqs_map[DDR_CH0] = {0, 3, 2, 1, 7, 5, 4, 6}, + .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 7, 6, 5}, + + /* Disable Early Command Training */ + .ect = 1, + + /* User Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &board_memcfg_cfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f01ad05dbff122534f1997e3f72e83b9333ffc0 Gerrit-Change-Number: 60241 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Add memory part and generate DRAM ID
by Teddy Shih (Code Review) 20 Dec '21

20 Dec '21

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60240 ) Change subject: mb/google/dedede/var/beadrix: Add memory part and generate DRAM ID ...................................................................... mb/google/dedede/var/beadrix: Add memory part and generate DRAM ID This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:204882915, b:210123929 BRANCH=None TEST=run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I28a12a6b23e15e424cf80a8d26948357a0282fd4 --- M src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc M src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/60240/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc old mode 100644 new mode 100755 index 6751a42..d513880 --- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt index fa24790..3af2e18 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -1 +1,3 @@ DRAM Part Name ID to assign +MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt old mode 100644 new mode 100755 index 9621137..ba69c43 --- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -1,11 +1,2 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name +MT53E512M32D1NP-046 WT:B +K4U6E3S4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/60240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a12a6b23e15e424cf80a8d26948357a0282fd4 Gerrit-Change-Number: 60240 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/futility: Ensure futility checks for flashrom as a dep
by Edward O'Callaghan (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Edward O'Callaghan, Julius Werner. Hello Hsuan-ting Chen, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60236 to look at the new patch set (#2). Change subject: util/futility: Ensure futility checks for flashrom as a dep ...................................................................... util/futility: Ensure futility checks for flashrom as a dep futility actually depends on flashrom. Previously it was of the form of subprocess and now uses the libflashrom API directly. Due to the previous subprocess decoupling it was not obvious that the dependency existed however not the runtime requirement is also a strict buildtime requirement. Therefore update the Makefile accordingly. BUG=b:203715651,b:209702505 TEST=builds Change-Id: Id9744424f75299eb8335c1c0c2aca2808bde829d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M util/futility/Makefile.inc 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/60236/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9744424f75299eb8335c1c0c2aca2808bde829d Gerrit-Change-Number: 60236 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings...
by Kenneth Chan (Code Review) 20 Dec '21

20 Dec '21

Kenneth Chan has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/60239 ) Change subject: mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for USB ports ...................................................................... mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for USB ports Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4). BUG=b:199468920 TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/60239/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 Gerrit-Change-Number: 60239 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021