coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/{adlrvp,sm}: Remove unused header `helpers.h`
by EricR Lai (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Nick Vaccaro, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60305 ) Change subject: mb/intel/{adlrvp,sm}: Remove unused header `helpers.h` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae Gerrit-Change-Number: 60305 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 03:23:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Hook up DPTF device to devicetree
by Felix Singer (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tim Crawford, Nico Huber, Patrick Rudolph, Jeremy Soller, Christian Walter, Tim Wawrzynczak, Michael Niewöhner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59887 ) Change subject: soc/intel/cannonlake: Hook up DPTF device to devicetree ...................................................................... Patch Set 11: (1 comment) File src/mainboard/google/hatch/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59887/comment/367c3142_4eb5d59b PS4, Line 204: device pci 04.0 on end # SA Thermal device > I moved the former two changes for separation into their own commit. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2ab7a691cb0f6941ef7c9def5fa2e6247127c15 Gerrit-Change-Number: 59887 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 03:13:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Fix DPTF device state in the devicetree on CFL boards
by Felix Singer (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tim Crawford, Nico Huber, Patrick Rudolph, Jeremy Soller, Tim Wawrzynczak, Christian Walter. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60203 ) Change subject: mainboard: Fix DPTF device state in the devicetree on CFL boards ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60203/comment/0149dab7_363dcf57 PS2, Line 14: Thus, set it to on to make the resource allocator aware of it. > Worth to mention in the commit message, IMHO. Or just rephrase. Currently […] Just copied the statement from below. Changes to the devicetree always have further implications. I haven't listed each side effect in any of my other patches hooking up the FSP options to the devicetree. Not sure why this is necessary here. -- To view, visit https://review.coreboot.org/c/coreboot/+/60203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561598c252c5da64ece569c6ba336852e713ccab Gerrit-Change-Number: 60203 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 03:08:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: add configuration for dojo
by Kevin Chiu (Code Review) 23 Dec '21

23 Dec '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60313 ) Change subject: mb/google/cherry: add configuration for dojo ...................................................................... mb/google/cherry: add configuration for dojo BUG=b:211528578 TEST=emerge-cherry coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: I3bd9803b4e47882df9fe351229478e4cb1630363 --- M src/mainboard/google/cherry/Kconfig M src/mainboard/google/cherry/Kconfig.name 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/60313/1 diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 7157267..8ef4a6e 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -36,6 +36,7 @@ config MAINBOARD_PART_NUMBER default "Cherry" if BOARD_GOOGLE_CHERRY + default "Dojo" if BOARD_GOOGLE_DOJO default "Tomato" if BOARD_GOOGLE_TOMATO config DRIVER_TPM_I2C_BUS diff --git a/src/mainboard/google/cherry/Kconfig.name b/src/mainboard/google/cherry/Kconfig.name index 7a65ada..9c58e51 100644 --- a/src/mainboard/google/cherry/Kconfig.name +++ b/src/mainboard/google/cherry/Kconfig.name @@ -4,6 +4,10 @@ bool "-> Cherry" select BOARD_GOOGLE_CHERRY_COMMON +config BOARD_GOOGLE_DOJO + bool "-> Dojo" + select BOARD_GOOGLE_CHERRY_COMMON + config BOARD_GOOGLE_TOMATO bool "-> Tomato" select BOARD_GOOGLE_CHERRY_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/60313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bd9803b4e47882df9fe351229478e4cb1630363 Gerrit-Change-Number: 60313 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Hung-Te Lin (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tianping Fang, Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60312 ) Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60312/comment/db7621c9_ac3b678f PS3, Line 9: a an https://review.coreboot.org/c/coreboot/+/60312/comment/6c46ae7a_ae481a4b PS3, Line 10: MT8195 can you explain why this is not a problem for 8183 and 8192? silicon design issue or? -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 02:57:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Hung-Te Lin, Tianping Fang, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60312 ) Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 02:45:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Hung-Te Lin, Tianping Fang, Yu-Ping Wu. Hello Hung-Te Lin, Tianping Fang, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60312 to look at the new patch set (#3). Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... soc/medaitek/mt8195: adjust USB phy shift value There is a issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefore, we add this patch to set USB phy registers from value of efuse. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Signed-off-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Tested-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 --- M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c M src/soc/mediatek/mt8195/include/soc/usb.h M src/soc/mediatek/mt8195/usb.c 4 files changed, 61 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/60312/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Hung-Te Lin, Tianping Fang, Yu-Ping Wu. Hello Hung-Te Lin, Tianping Fang, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60312 to look at the new patch set (#2). Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... soc/medaitek/mt8195: adjust USB phy shift value There is a issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefor we add this patch to set USB phy register from value of efuse setting. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Signed-off-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Tested-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 --- M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c M src/soc/mediatek/mt8195/include/soc/usb.h M src/soc/mediatek/mt8195/usb.c 4 files changed, 61 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/60312/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Rename ADL_P_482_CORE to ADL_P_482_28W_CORE
by Curtis Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Kane Chen, Curtis Chen, Patrick Rudolph. Hello V Sowmya, build bot (Jenkins), Tim Wawrzynczak, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60267 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Rename ADL_P_482_CORE to ADL_P_482_28W_CORE ...................................................................... soc/intel/alderlake: Rename ADL_P_482_CORE to ADL_P_482_28W_CORE The VR config items differ between ADL-P 4+8+2 28W and 45W. The current settings are for ADL-P 4+8+2 28W, so rename the enum member. BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: I863023eba5fda3b6d45059383d6030427913ca9a --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/60267/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I863023eba5fda3b6d45059383d6030427913ca9a Gerrit-Change-Number: 60267 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tianping Fang. Hello Tianping Fang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60312 to review the following change. Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... soc/medaitek/mt8195: adjust USB phy shift value There is a issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefor we add this patch to set USB phy register from value of efuse setting. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Signed-off-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Test-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 --- M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c M src/soc/mediatek/mt8195/include/soc/usb.h M src/soc/mediatek/mt8195/usb.c 4 files changed, 61 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/60312/1 diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index 6fa050d..d390b70 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -130,9 +130,13 @@ check_member(sif_u2_phy_com, u2phydtm0, 0x68); struct sif_u3phyd { - u32 reserved0[23]; + u32 reserved0[4]; + u32 phyd_cal0; + u32 phyd_cal1; + u32 reserved1[15]; + u32 phyd_reserved; u32 phyd_cdr1; - u32 reserved1[40]; + u32 reserved2[41]; }; struct sif_u3phya { @@ -155,6 +159,7 @@ * SOCs will not need it. */ void mtk_usb_prepare(void); +void mtk_usb_adjust_phy_shift(void); void setup_usb_host(void); diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index 52daaac..b9fe835 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -140,7 +140,15 @@ clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); } -__weak void mtk_usb_prepare(void) { /* do nothing */ } +__weak void mtk_usb_prepare(void) +{ + /* do nothing */ +} + +__weak void mtk_usb_adjust_phy_shift(void) +{ + /* do nothing */ +} void setup_usb_host(void) { @@ -153,5 +161,6 @@ return; } u3phy_power_on(); + mtk_usb_adjust_phy_shift(); u3p_msg("phy power-on done.\n"); } diff --git a/src/soc/mediatek/mt8195/include/soc/usb.h b/src/soc/mediatek/mt8195/include/soc/usb.h index e39ec38..c3b3c58 100644 --- a/src/soc/mediatek/mt8195/include/soc/usb.h +++ b/src/soc/mediatek/mt8195/include/soc/usb.h @@ -19,6 +19,21 @@ check_member(ssusb_sif_port, u3phya_da, 0x900); check_member(ssusb_sif_port, reserved2, 0xa00); -#define USB_PORT_NUMBER 1 +DEFINE_BIT(AUTO_LOAD_DIS, 12) +DEFINE_BITFIELD(TX_IMP_CAL, 28, 24) +DEFINE_BIT(TX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(RX_IMP_CAL, 28, 24) +DEFINE_BIT(RX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(INTR_CAL, 15, 10) + +#define TX_IMP_MASK 0x1F +#define TX_IMP_SHIFT 0 +#define RX_IMP_MASK 0x3E0 +#define RX_IMP_SHIFT 5 +#define INTR_CAL_MASK 0xFC00 +#define INTR_CAL_SHIFT 10 + +#define USB_PHY_SETTING_REG 0x11C10184 +#define USB_PORT_NUMBER 1 #endif diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c index 7b6347e..b3f00a9 100644 --- a/src/soc/mediatek/mt8195/usb.c +++ b/src/soc/mediatek/mt8195/usb.c @@ -10,3 +10,31 @@ setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15)); setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31)); } + +void mtk_usb_adjust_phy_shift(void) +{ + u32 phy_set_val, write_val; + struct ssusb_sif_port *phy = (void *)(SSUSB_SIF_BASE); + + SET32_BITFIELDS(&phy->u3phyd.phyd_reserved, + AUTO_LOAD_DIS, 1); + + phy_set_val = read32((void *)USB_PHY_SETTING_REG); + + /* TX imp */ + write_val = (phy_set_val & TX_IMP_MASK) >> TX_IMP_SHIFT; + SET32_BITFIELDS(&phy->u3phyd.phyd_cal0, + TX_IMP_CAL, write_val, + TX_IMP_CAL_EN, 1); + + /* RX imp */ + write_val = (phy_set_val & RX_IMP_MASK) >> RX_IMP_SHIFT; + SET32_BITFIELDS(&phy->u3phyd.phyd_cal1, + RX_IMP_CAL, write_val, + RX_IMP_CAL_EN, 1); + + /* Intr_cal */ + write_val = (phy_set_val & INTR_CAL_MASK) >> INTR_CAL_SHIFT; + SET32_BITFIELDS(&phy->u3phya.phya_reg0, + INTR_CAL, write_val); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021