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Change subject: mb/google/brya: Add new baseboard nissa with variants nivviks and nereid
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/brya: Add new baseboard nissa with variants nivviks and nereid
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/60271/comment/c8d8608b_7e7ca405
PS3, Line 20: def_bool n
> nit: def_bool typically goes before select
Done
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Hello build bot (Jenkins), Reka Norman, Subrata Banik, Kangheui Won, Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60271
to look at the new patch set (#4).
Change subject: mb/google/brya: Add new baseboard nissa with variants nivviks and nereid
......................................................................
mb/google/brya: Add new baseboard nissa with variants nivviks and nereid
Add a new baseboard for nissa, an Intel ADL-N based reference design.
Also add variants for the two reference boards, nivviks and nereid.
This commit is a stub which only adds the minimum code needed for a
successful build.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
abuild -a -x -c max -p none -t google/brya -b nereid
Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc
A src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
A src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
A src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h
A src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
A src/mainboard/google/brya/variants/baseboard/nissa/memory.c
A src/mainboard/google/brya/variants/nereid/include/variant/ec.h
A src/mainboard/google/brya/variants/nereid/include/variant/gpio.h
A src/mainboard/google/brya/variants/nereid/overridetree.cb
A src/mainboard/google/brya/variants/nivviks/include/variant/ec.h
A src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h
A src/mainboard/google/brya/variants/nivviks/overridetree.cb
14 files changed, 182 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/60271/4
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Change subject: ChromeOS: Refactor ACPI CNVS generation
......................................................................
Patch Set 18:
(1 comment)
Patchset:
PS15:
> Of course. I think CB:58421 has the problematic \CRHW to \_SB. […]
cool thanks! it's not that I don't want to fix it, it's just low on my list of things to do 😊
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Change subject: mb/google/brya/var/taniks: Include driver for GL9763E for eMMC boot disk
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/brya/var/brask: Customize LEDs of RT8125
......................................................................
Patch Set 2: Code-Review+2
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Change subject: drivers/net/r8168: Modify to support RTL8125 LEDs
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Patch Set 6: Code-Review+2
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Change subject: mb/google/brya: Add new baseboard nissa with variants nivviks and nereid
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/60271/comment/f558cc41_010b4b75
PS3, Line 20: def_bool n
nit: def_bool typically goes before select
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Change subject: [WIP] cpu/x86/lapic: Fix choice X2APIC_ONLY
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60213/comment/c8b7888c_cfe0fbef
PS2, Line 11: avoid entering a printk() and acquiring console_lock and
: dead-locking.
> just to be clear, have you observed this happening before?
We have similar comments in lapic_cpu_stop.c:stop_this_cpu(). The comments and current implementation is mine, but it originates way back, CB:776.
Maybe there is some more proper way, like some fence or other barrier?
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/60213/comment/da03288e_84a12c43
PS2, Line 652: lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid());
> it looks like this is the only place we send IPI to self. […]
We can do that. There is also stop_this_cpu(), like mentioned before.
I will try if the delay is still necessary if we use the "Self IPI" destination shorthand that does not require passing the target APIC ID.
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Change subject: mb/google/brya/var/primus: Follow the schematic to modify the gpio pin to none.
......................................................................
Patch Set 12:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60104/comment/9fe5c1f0_214897c2
PS9, Line 9: - Modify the gpio pin to none.
> Explain the issue and why this patch fixes the issue.
I think what we're getting at here is a few GPIOs were missed during the initial review, and this fixes those oversights.
https://review.coreboot.org/c/coreboot/+/60104/comment/1fb3aa6d_06400d3c
PS9, Line 11: B
> Missing number?
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/60104/comment/84dc80a7_c626ff71
PS12, Line 7: Follow the schematic to modify the gpio pin to none.
suggestion:
```
mb/google/brya/var/primus: Fix some GPIO programming
During the initial review, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
```
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