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Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak,
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Change subject: mb/google/brya/var/taeko4es: Set vGPIO reset type
......................................................................
mb/google/brya/var/taeko4es: Set vGPIO reset type
Copied from commit df72b18d (mb/google/brya/var/taeko: Set vGPIO reset
type).Due to the vGPIO is not reset when we power on through S5, we
would met MCA when PCIE send L1 request without following Ack.
BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782
---
M src/mainboard/google/brya/variants/taeko4es/gpio.c
1 file changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/60186/3
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Ariel Fang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60104 )
Change subject: mb/google/brya/var/primus:Fix some GPIO programming
......................................................................
Patch Set 14:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60104/comment/b0a4c469_abb2d0b4
PS9, Line 7: Modify the GPIO pin to none.
> You are modifying multiple pads, and also adding new. […]
Done
https://review.coreboot.org/c/coreboot/+/60104/comment/c54d8279_c8df941e
PS9, Line 9: - Modify the gpio pin to none.
> I think what we're getting at here is a few GPIOs were missed during the initial review, and this fi […]
done,thanks Tim.thanks Felix. 😊
Commit Message:
https://review.coreboot.org/c/coreboot/+/60104/comment/403f5c7f_3faeeaab
PS12, Line 7: Follow the schematic to modify the gpio pin to none.
> suggestion: […]
Done
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#14).
Change subject: mb/google/brya/var/primus:Fix some GPIO programming
......................................................................
mb/google/brya/var/primus:Fix some GPIO programming
-During the initial review, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
GPP_B5 => I2C
GPP_B6 => I2C
GPP_B15 => non-use (for FPR)
GPP_D3 => non-use ( Test point)
GPP_E21 => non-use (for LCLW Detect)
BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot and verify it builds without error.
Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 21 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60104/14
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60104
to look at the new patch set (#13).
Change subject: mb/google/brya/var/primus: Fix some GPIO programming
......................................................................
mb/google/brya/var/primus: Fix some GPIO programming
-During the initial review, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
GPP_B5 => I2C
GPP_B6 => I2C
GPP_B15 => non-use (for FPR)
GPP_D3 => non-use ( Test point)
GPP_E21 => non-use (for LCLW Detect)
BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot and verify it builds without error.
Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 21 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60104/13
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: add variant_gpio_lock_config()
......................................................................
mb/google/brya: add variant_gpio_lock_config()
Add variant_gpio_lock_config() to give variants a way to provide a list
of gpios that the variant wants locked, such as gpios connected to the
TPM.
BUG=b:208827718
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0
to kernel.
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: I3edc309335b2751a85b479250ee0c470ea842c2e
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/common/block/smm/smihandler.c
4 files changed, 65 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60274/5
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Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60274
to look at the new patch set (#4).
Change subject: soc/intel/common/block/gpio: add variant_gpio_lock_config()
......................................................................
soc/intel/common/block/gpio: add variant_gpio_lock_config()
Add variant_gpio_lock_config() to give variants a way to provide a list
of gpios that the variant wants locked, such as gpios connected to the
TPM.
BUG=b:208827718
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0
to kernel.
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: I3edc309335b2751a85b479250ee0c470ea842c2e
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/common/block/smm/smihandler.c
4 files changed, 65 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60274/4
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59556 )
Change subject: src/mainboard/herobrine: Add support QUP FW for I2C and SPI
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Should this CL be merged with https://review.coreboot.org/c/coreboot/+/50581 ?
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Change subject: Herobrine: TPM Config Changes to support audio
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60167/comment/e273c719_e2d47dd1
PS2, Line 7: to support audio
This doesn't have to do with audio support. This is just configuring the TPM interrupt GPIO.
https://review.coreboot.org/c/coreboot/+/60167/comment/cccf7e3c_7cd84d83
PS2, Line 9: Add configuration for target specific i2s ports
This is not i2s related.
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Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60274
to look at the new patch set (#3).
Change subject: soc/intel/common/block/gpio: add variant_gpio_lock_config()
......................................................................
soc/intel/common/block/gpio: add variant_gpio_lock_config()
Add variant_gpio_lock_config() to give variants a way to provide a list
of gpios that the variant wants locked, such as gpios connected to the
TPM.
BUG=b:208827718
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0
to kernel.
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: I3edc309335b2751a85b479250ee0c470ea842c2e
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/common/block/smm/smihandler.c
4 files changed, 69 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60274/3
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