coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: device: Make pciexp_get_ltr_max_latencies a public function
by 9elements QA (Code Review) 22 Dec '21

22 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60015 ) Change subject: device: Make pciexp_get_ltr_max_latencies a public function ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 4 / 4 / 8 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/85522 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/85521 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/85520 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/85519 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/85518 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/85517 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/85516 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/85515 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/60015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Gerrit-Change-Number: 60015 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 18:46:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: Add Hynix LP5 DRAM support
by Tim Wawrzynczak (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Kevin Chiu, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60288 ) Change subject: mb/google/brya/var/vell: Add Hynix LP5 DRAM support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e Gerrit-Change-Number: 60288 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 22 Dec 2021 18:42:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable Bayhub LV2 driver
by Tim Wawrzynczak (Code Review) 22 Dec '21

22 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60017 ) Change subject: mb/google/brya/var/taeko: Enable Bayhub LV2 driver ...................................................................... mb/google/brya/var/taeko: Enable Bayhub LV2 driver Some SKUs of google/taeko have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:204343849 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/60017 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Nick Vaccaro: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index b73657c..9f7f75a 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -98,6 +98,7 @@ bool "-> Taeko" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9763E + select DRIVERS_GENERIC_BAYHUB_LV2 config BOARD_GOOGLE_TAEKO4ES bool "-> Taeko4ES" -- To view, visit https://review.coreboot.org/c/coreboot/+/60017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac Gerrit-Change-Number: 60017 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/generic/bayhub_lv2: Work around known errata
by Tim Wawrzynczak (Code Review) 22 Dec '21

22 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60016 ) Change subject: drivers/generic/bayhub_lv2: Work around known errata ...................................................................... drivers/generic/bayhub_lv2: Work around known errata The Bayhub LV2 has a known errata wherein PCI config registers at offsets 0x234, 0x238, and 0x24C will only correctly accept writes when they are addressed via a DWORD (32-bit) wide write operation on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop latency register, therefore add a finalize callback to this driver which will program the LTR max-snoop/no-snoop register with a 32-bit write using the values from pciexp_get_ltr_max_latencies(). BUG=b:204343849 TEST=verified the PCI config space writes took effect on google/taeko Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60016 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/drivers/generic/bayhub_lv2/lv2.c 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Nick Vaccaro: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c index 90e1e5d..7cd8a36 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.c +++ b/src/drivers/generic/bayhub_lv2/lv2.c @@ -6,11 +6,32 @@ #include <device/device.h> #include <device/path.h> #include <device/pci.h> +#include <device/pciexp.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include "chip.h" #include "lv2.h" +/* + * This chip has an errata where PCIe config space registers 0x234, 0x248, and + * 0x24C only support DWORD access, therefore reprogram these in the `finalize` + * callback. + */ +static void lv2_enable_ltr(struct device *dev) +{ + u16 max_snoop, max_nosnoop; + if (!pciexp_get_ltr_max_latencies(dev, &max_snoop, &max_nosnoop)) + return; + + const unsigned int ltr_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID); + if (!ltr_cap) + return; + + pci_write_config32(dev, ltr_cap + PCI_LTR_MAX_SNOOP, (max_snoop << 16) | max_nosnoop); + printk(BIOS_INFO, "%s: Re-programmed LTR max latencies using chip-specific quirk\n", + dev_path(dev)); +} + static void lv2_enable(struct device *dev) { struct drivers_generic_bayhub_lv2_config *config = dev->chip_info; @@ -45,6 +66,7 @@ .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, .enable = lv2_enable, + .final = lv2_enable_ltr, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/60016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517 Gerrit-Change-Number: 60016 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/gpio: add variant_gpio_lock_config()
by Nick Vaccaro (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60274 ) Change subject: soc/intel/common/block/gpio: add variant_gpio_lock_config() ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Yes, but that is also how we handle, e.g., GPIOs. […] To do that, we either change the api for mb_gpio_lock_config() to allow a second list ptr to be passed back, or we have to allocate memory in mb_gpio_lock_config() to hold both mb and variant list, concatenate them there and pass the pointer back from mb_gpio_lock_config(), but then caller of mb_gpio_lock_config() must free the memory after locking the list of gpios. Non-optimal issue with that is that if variant doesn't export a list, mb_gpio_lock_config() will still need to allocate a block of memory and copy its own list into it. Thoughts on the best / most efficient way to implement this? -- To view, visit https://review.coreboot.org/c/coreboot/+/60274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3edc309335b2751a85b479250ee0c470ea842c2e Gerrit-Change-Number: 60274 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 18:32:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: HACK: Herobrine: Reinit TPM INT gpio after qclib executes
by Shelley Chen (Code Review) 22 Dec '21

22 Dec '21

Shelley Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57025 ) Change subject: HACK: Herobrine: Reinit TPM INT gpio after qclib executes ...................................................................... Abandoned This is not needed anymore -- To view, visit https://review.coreboot.org/c/coreboot/+/57025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c43d120ebb49800c82aec263ff8c215b60c5201 Gerrit-Change-Number: 57025 Gerrit-PatchSet: 38 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: HACK: Herobrine: Reinit TPM INT GPIO
by Shelley Chen (Code Review) 22 Dec '21

22 Dec '21

Shelley Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57022 ) Change subject: HACK: Herobrine: Reinit TPM INT GPIO ...................................................................... Abandoned This is not needed anymore -- To view, visit https://review.coreboot.org/c/coreboot/+/57022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30426cc0392a640fb6d3b1d0fafca7e9a67a76c3 Gerrit-Change-Number: 57022 Gerrit-PatchSet: 38 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: crossgcc/buildgcc: Remove unused GCC_AUTOCONF_VERSION
by HAOUAS Elyes (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Paul Menzel. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59398 ) Change subject: crossgcc/buildgcc: Remove unused GCC_AUTOCONF_VERSION ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59398/comment/00fbe270_ca4704ac PS2, Line 7: Clean-up > Please use your summary below: […] Ack https://review.coreboot.org/c/coreboot/+/59398/comment/aebb9a96_8f5fa9b4 PS2, Line 10: > Please add: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d293ae2c8663efdc9ad4146ff32671ffd3e176a Gerrit-Change-Number: 59398 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 18:27:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc/Makefile: Remove obsolete target build_make
by HAOUAS Elyes (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Paul Menzel. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59397 ) Change subject: crossgcc/Makefile: Remove obsolete target build_make ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59397/comment/a01f054a_58927404 PS2, Line 7: Clean-up > Remove obsolete target build_make Ack https://review.coreboot.org/c/coreboot/+/59397/comment/35755fd7_d2c4398a PS2, Line 9: coreboot do not build "Make" anymore. > Since what commit? Ack https://review.coreboot.org/c/coreboot/+/59397/comment/d819c0fe_31d0a48b PS2, Line 9: do > does Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f159fc912d09ebde6ac7ba5be83933aa251f1d5 Gerrit-Change-Number: 59397 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 18:25:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: device: Make pciexp_get_ltr_max_latencies a public function
by Subrata Banik (Code Review) 22 Dec '21

22 Dec '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60015 ) Change subject: device: Make pciexp_get_ltr_max_latencies a public function ...................................................................... device: Make pciexp_get_ltr_max_latencies a public function Some device drivers may need to get access to the LTR values for their respective devices, therefore export this function instead of marking it static. BUG=b:204343849 Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60015 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/device/pciexp_device.c M src/include/device/pciexp.h 2 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index d8ed5d9..5e2709e 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -181,7 +181,7 @@ (void)_pciexp_enable_ltr(parent, parent_cap, dev, cap); } -static bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop) +bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop) { /* Walk the hierarchy up to find get_ltr_max_latencies(). */ do { diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index fbc769e..756733e 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -39,4 +39,6 @@ type == PCI_EXP_TYPE_PCIE_BRIDGE; } +bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop); + #endif /* DEVICE_PCIEXP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Gerrit-Change-Number: 60015 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021