coreboot-gerrit December 2021

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Change in coreboot[master]: device: Make pciexp_get_ltr_max_latencies a public function
by Subrata Banik (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60015 ) Change subject: device: Make pciexp_get_ltr_max_latencies a public function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Gerrit-Change-Number: 60015 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 18:13:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function
by Tim Crawford (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Cliff Huang, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60179 ) Change subject: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Gerrit-Change-Number: 60179 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 18:01:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs
by Tim Crawford (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Cliff Huang, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60183 ) Change subject: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: > Hey Tim any chance you could try this patch (and CB:60179) on one of your TGL boards that uses a PEG […] I don't see any issues on galp5 or oryp8. -- To view, visit https://review.coreboot.org/c/coreboot/+/60183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Gerrit-Change-Number: 60183 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 18:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/gpio: add variant_gpio_lock_config()
by Tim Wawrzynczak (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60274 ) Change subject: soc/intel/common/block/gpio: add variant_gpio_lock_config() ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I thought about that, but that would mean that that mechanism will have to be reproduced for each in […] Yes, but that is also how we handle, e.g., GPIOs. We so far have not let any variant-specific callbacks, etc. into common code. -- To view, visit https://review.coreboot.org/c/coreboot/+/60274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3edc309335b2751a85b479250ee0c470ea842c2e Gerrit-Change-Number: 60274 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 17:43:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: google/herobrine: configure gpio to detect board ID.
by Shelley Chen (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Ravi kumar, Ravi Kumar Bokka, Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56642 ) Change subject: google/herobrine: configure gpio to detect board ID. ...................................................................... Patch Set 36: (12 comments) File src/mainboard/google/herobrine/boardid.c: https://review.coreboot.org/c/coreboot/+/56642/comment/2a03d774_5c9bd3ca PS36, Line 14: if (CONFIG(BOARD_GOOGLE_HEROBRINE)){ > space required before the open brace '{' Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/e42ca6f3_15e4c3be PS36, Line 19: else if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) || CONFIG(BOARD_GOOGLE_SENOR)){ > space required before the open brace '{' Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/b34320b2_776ec6b2 PS36, Line 19: else if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) || CONFIG(BOARD_GOOGLE_SENOR)){ > else should follow close brace '}' Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/cfd23613_6d30186d PS36, Line 19: else if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) || CONFIG(BOARD_GOOGLE_SENOR)){ > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/69ae0254_656f4794 PS36, Line 20: pins[2] = GPIO(50); > please, no spaces at the start of a line Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/9dd9c387_2c4a2c3f PS36, Line 20: pins[2] = GPIO(50); > code indent should use tabs where possible Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/d94dfce6_f81fd329 PS36, Line 21: pins[1] = GPIO(49); > please, no spaces at the start of a line Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/09e71e0e_c4f1095a PS36, Line 21: pins[1] = GPIO(49); > code indent should use tabs where possible Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/04668d19_1fbd92ea PS36, Line 22: pins[0] = GPIO(48); > code indent should use tabs where possible Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/42dc0cb0_6ec0d09e PS36, Line 22: pins[0] = GPIO(48); > please, no spaces at the start of a line Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/402f01a6_93160556 PS36, Line 26: if (id == UNDEFINED_STRAPPING_ID){ > braces {} are not necessary for single statement blocks Please fix. https://review.coreboot.org/c/coreboot/+/56642/comment/93fde59e_55af16c9 PS36, Line 26: if (id == UNDEFINED_STRAPPING_ID){ > space required before the open brace '{' Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/56642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 Gerrit-Change-Number: 56642 Gerrit-PatchSet: 36 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 17:40:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable Bayhub LV2 driver
by Karthik Ramasubramanian (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Kevin Chang, Tim Wawrzynczak. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60017 ) Change subject: mb/google/brya/var/taeko: Enable Bayhub LV2 driver ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac Gerrit-Change-Number: 60017 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 17:37:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/generic/bayhub_lv2: Work around known errata
by Karthik Ramasubramanian (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Tim Wawrzynczak. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60016 ) Change subject: drivers/generic/bayhub_lv2: Work around known errata ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517 Gerrit-Change-Number: 60016 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 17:36:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: Make pciexp_get_ltr_max_latencies a public function
by Karthik Ramasubramanian (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Tim Wawrzynczak. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60015 ) Change subject: device: Make pciexp_get_ltr_max_latencies a public function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Gerrit-Change-Number: 60015 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 17:35:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: Make pciexp_get_ltr_max_latencies a public function
by Subrata Banik (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Tim Wawrzynczak, Karthik Ramasubramanian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60015 ) Change subject: device: Make pciexp_get_ltr_max_latencies a public function ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Not having +2 vote right yet, hence +1 max I could support for this CL 😭 -- To view, visit https://review.coreboot.org/c/coreboot/+/60015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Gerrit-Change-Number: 60015 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 22 Dec 2021 17:23:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/gpio: add variant_gpio_lock_config()
by Nick Vaccaro (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60274 ) Change subject: soc/intel/common/block/gpio: add variant_gpio_lock_config() ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Instead of yet another list, I think this delegation to the variant should happen at the mainboard l […] I thought about that, but that would mean that that mechanism will have to be reproduced for each intel mainboard that wants to use gpio locking for variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/60274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3edc309335b2751a85b479250ee0c470ea842c2e Gerrit-Change-Number: 60274 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 22 Dec 2021 17:15:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit December 2021