Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55503 )
Change subject: util/cse_serger: Add a new tool for stitching CSE components
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Patch Set 31:
(1 comment)
Patchset:
PS31:
isn't this redundant to ifwitool, at least parly? (I just had a very rough look tbh)
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60203 )
Change subject: mainboard: Fix DPTF device state in the devicetree on CFL boards
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Patch Set 2: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60203/comment/f53803e1_41b5b0c6
PS2, Line 12: * google/hatch
> As Tim wrote, he tested google/dratini. […]
Done
Wording could be better though, currently it suggests all of hatch is affected.
https://review.coreboot.org/c/coreboot/+/60203/comment/92c6e6ff_3e2859bb
PS2, Line 14: Thus, set it to on to make the resource allocator aware of it.
> Anything to do here?
Worth to mention in the commit message, IMHO. Or just rephrase. Currently
it suggests to me that the resource allocation is the only difference. While
it's just one of many side effects.
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Change subject: HACK: Herobrine: Reinit TPM INT gpio after qclib executes
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Patch Set 38: Verified-1
(2 comments)
File src/soc/qualcomm/common/qclib.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136040):
https://review.coreboot.org/c/coreboot/+/57025/comment/64c0b5b4_b9be7e2d
PS38, Line 254: mainboard_blob_fix();
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136040):
https://review.coreboot.org/c/coreboot/+/57025/comment/c4509916_eb25758c
PS38, Line 254: mainboard_blob_fix();
please, no spaces at the start of a line
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Change subject: libpayload: Parse DDR Information through coreboot tables
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Patch Set 8: Verified-1
(1 comment)
File payloads/libpayload/include/mem_chip_info.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136034):
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PS8, Line 44: }dram_info;
space required after that close brace '}'
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Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot.
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Patch Set 13: Verified-1
(1 comment)
File src/soc/qualcomm/sc7280/soc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136031):
https://review.coreboot.org/c/coreboot/+/58545/comment/daf09d79_3b2ae810
PS13, Line 27: if (soc_modem_carve_out(&start, &end))
that open brace { should be on the previous line
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Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60186
to look at the new patch set (#2).
Change subject: mb/google/brya/var/taeko4es: Set vGPIO reset type
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mb/google/brya/var/taeko4es: Set vGPIO reset type
Copied from commit df72b18d. Due to the vGPIO is not reset when we power
on through S5, we would met MCA when PCIE send L1 request without
following Ack.
BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782
---
M src/mainboard/google/brya/variants/taeko4es/gpio.c
1 file changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/60186/2
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