coreboot-gerrit December 2021

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Change in coreboot[master]: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
by Sudheer Amrabadi (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Ravi kumar, Shelley Chen, Sudheer Amrabadi, Julius Werner, Yu-Ping Wu. Sudheer Amrabadi has uploaded a new patch set (#210) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/36278 ) Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK ...................................................................... HACK trogdor: optimize coreboot.rom for T32 flash script HACK Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- A 0001-google-herobrine-configure-gpio-to-detect-board-ID.patch A 0002-mb-google-herobrine-Initialize-SPI-FW-for-EC-and-TPM.patch A 0003-Herobrine-sc7280-Add-support-for-audio.patch A 0004-Herobrine-TPM-Config-Changes-to-support-audio.patch A 0005-sc7280-enable-bl31-and-SDI-feature-support.patch A 0006-sc7280-Add-Modem-region-in-memlayout-to-avoid-modem-.patch A 0007-sc7180-Update-video-mode-active-horizontal-vertical-.patch A 0008-src-mainboard-herobrine-Add-support-QUP-FW-for-I2C-a.patch A 0009-libpayload-Parse-DDR-Information-through-coreboot-ta.patch A 0010-src-lib-Added-CBMEM-tag-id-to-parse-ddr-information.patch A 0011-soc-Added-dram-information-to-cbmem.patch A 0012-HACK-Senor-build-support-HACK.patch A 0013-HACK-sc7280-QSIP-SPI-NOR-addressing-mode-for-SKU1-an.patch A 0014-HACK-Herobrine-Reinit-TPM-INT-GPIO.patch A 0015-HACK-Herobrine-Reinit-TPM-INT-gpio-after-qclib-execu.patch A 0016-HACK-herobrine-T32-scripts-working-in-standalone-env.patch A 0017-HACK-trogdor-optimize-coreboot.rom-for-T32-flash-scr.patch M src/security/vboot/Makefile.inc A util/qualcomm/optimize_coreboot 19 files changed, 1,441 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36278/210 -- To view, visit https://review.coreboot.org/c/coreboot/+/36278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Gerrit-Change-Number: 36278 Gerrit-PatchSet: 210 Gerrit-Owner: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/magolor: Add initial CdClock value
by Ren Kuo (Code Review) 22 Dec '21

22 Dec '21

Ren Kuo has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Add initial CdClock value ...................................................................... mb/google/dedede/var/magolor: Add initial CdClock value Add initial CdClock value to get more stable boot up in OS. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode. Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60301/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/magolor: Add initial CdClock value
by Ren Kuo (Code Review) 22 Dec '21

22 Dec '21

Ren Kuo has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Add initial CdClock value ...................................................................... mb/google/dedede/var/magolor: Add initial CdClock value Add CdClock initial value to get more stable boot up in OS. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode. Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60301/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/magolor: Add CdClock initial value
by Ren Kuo (Code Review) 22 Dec '21

22 Dec '21

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Add CdClock initial value ...................................................................... mb/google/dedede/var/magolor: Add CdClock initial value Add CdClock initial value to get more stable boot up in OS. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode. Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60301/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 2a07f45..6583d01 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -107,6 +107,9 @@ register "SlowSlewRate" = "SlewRateFastBy8" register "FastPkgCRampDisable" = "1" + # Core Display Clock Frequency selection + register "CdClock" = "0x0" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: CB patch-train re-ordered/updated and pushed upstream
by Sudheer Amrabadi (Code Review) 22 Dec '21

22 Dec '21

Sudheer Amrabadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60300 ) Change subject: CB patch-train re-ordered/updated and pushed upstream ...................................................................... CB patch-train re-ordered/updated and pushed upstream * CB: - mb/google/herobrine: Initialize SPI FW for EC and TPM - google/herobrine: configure gpio to detect board ID. Change-Id: I7f0e406d5adbc1b7502a12f15658fd0e236b3bfe Signed-off-by: Sudheer kumar amrabadi <samrabad(a)codeaurora.org> --- A 0001-google-herobrine-configure-gpio-to-detect-board-ID.patch A 0002-mb-google-herobrine-Initialize-SPI-FW-for-EC-and-TPM.patch A 0003-Herobrine-sc7280-Add-support-for-audio.patch A 0004-Herobrine-TPM-Config-Changes-to-support-audio.patch A 0005-sc7280-enable-bl31-and-SDI-feature-support.patch A 0006-sc7280-Add-Modem-region-in-memlayout-to-avoid-modem-.patch A 0007-sc7180-Update-video-mode-active-horizontal-vertical-.patch A 0008-src-mainboard-herobrine-Add-support-QUP-FW-for-I2C-a.patch A 0009-libpayload-Parse-DDR-Information-through-coreboot-ta.patch A 0010-src-lib-Added-CBMEM-tag-id-to-parse-ddr-information.patch A 0011-soc-Added-dram-information-to-cbmem.patch A 0012-HACK-Senor-build-support-HACK.patch A 0013-HACK-sc7280-QSIP-SPI-NOR-addressing-mode-for-SKU1-an.patch A 0014-HACK-Herobrine-Reinit-TPM-INT-GPIO.patch A 0015-HACK-Herobrine-Reinit-TPM-INT-gpio-after-qclib-execu.patch A 0016-HACK-herobrine-T32-scripts-working-in-standalone-env.patch A 0017-HACK-trogdor-optimize-coreboot.rom-for-T32-flash-scr.patch 17 files changed, 1,439 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60300/1 diff --git a/0001-google-herobrine-configure-gpio-to-detect-board-ID.patch b/0001-google-herobrine-configure-gpio-to-detect-board-ID.patch new file mode 100644 index 0000000..1dbc24d --- /dev/null +++ b/0001-google-herobrine-configure-gpio-to-detect-board-ID.patch @@ -0,0 +1,72 @@ +From ef36e58bc0c01b1fa4603473042a2906ba74ac31 Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Tue, 27 Jul 2021 19:29:18 +0530 +Subject: [PATCH 01/17] google/herobrine: configure gpio to detect board ID. + +BUG=b:182963902, b:193807794 +TEST=Validated on qualcomm sc7280 development board + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 +--- + src/mainboard/google/herobrine/board.h | 1 - + src/mainboard/google/herobrine/boardid.c | 28 +++++++++++++++++----------- + 2 files changed, 17 insertions(+), 12 deletions(-) + +diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h +index 4278c11..367334a 100644 +--- a/src/mainboard/google/herobrine/board.h ++++ b/src/mainboard/google/herobrine/board.h +@@ -18,7 +18,6 @@ + + #define QCOM_SC7280_SKU1 0x0 + #define QCOM_SC7280_SKU2 0x1 +-#define QCOM_SC7280_SKU3 0x2 + + /* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */ + #if CONFIG(HEROBRINE_HAS_FINGERPRINT) +diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c +index 7db3e0b..a8ff3bf 100644 +--- a/src/mainboard/google/herobrine/boardid.c ++++ b/src/mainboard/google/herobrine/boardid.c +@@ -10,20 +10,26 @@ + uint32_t board_id(void) + { + static uint32_t id = UNDEFINED_STRAPPING_ID; +- const gpio_t pins[] = {[2] = GPIO(50), [1] = GPIO(49), [0] = GPIO(48)}; +- +- if (id == UNDEFINED_STRAPPING_ID) ++ gpio_t pins[3]; ++ if (CONFIG(BOARD_GOOGLE_HEROBRINE)){ ++ pins[2] = GPIO(75); ++ pins[1] = GPIO(74); ++ pins[0] = GPIO(73); ++ } ++ else if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) || CONFIG(BOARD_GOOGLE_SENOR)){ ++ pins[2] = GPIO(50); ++ pins[1] = GPIO(49); ++ pins[0] = GPIO(48); ++ ++ } ++ ++ if (id == UNDEFINED_STRAPPING_ID){ + id = gpio_base3_value(pins, ARRAY_SIZE(pins)); +- +- if ((id == QCOM_SC7280_SKU1) || (id == QCOM_SC7280_SKU2) || +- (id == QCOM_SC7280_SKU3)) +- printk(BIOS_INFO, "BoardID :%d - " ++ } ++ printk(BIOS_INFO, "BoardID :%d - " + "Machine model: " + "Qualcomm Technologies, Inc. " +- "sc7280 IDP SKU%d platform\n", id, (id+1)); +- else +- printk(BIOS_ERR, "Invalid BoardId : %d\n", id); +- ++ "sc7280 platform\n", id); + return id; + } + +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0002-mb-google-herobrine-Initialize-SPI-FW-for-EC-and-TPM.patch b/0002-mb-google-herobrine-Initialize-SPI-FW-for-EC-and-TPM.patch new file mode 100644 index 0000000..bfb170b --- /dev/null +++ b/0002-mb-google-herobrine-Initialize-SPI-FW-for-EC-and-TPM.patch @@ -0,0 +1,148 @@ +From 17689b4ebfb70689b5d196cc67d7577b2b4a294b Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Wed, 29 Sep 2021 22:42:20 +0530 +Subject: [PATCH 02/17] mb/google/herobrine: Initialize SPI FW for EC and TPM + +Initialize SPI firmware for EC and H1/TPM instances for Piglin and Hoglin. +Load QUP FW in respective Serial Engines. + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 developement board + +Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c +Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> +--- + src/mainboard/google/herobrine/Kconfig | 22 +++++++++++++++++++++- + src/mainboard/google/herobrine/board.h | 15 +++++++++++++++ + src/mainboard/google/herobrine/bootblock.c | 11 +++++++++++ + src/mainboard/google/herobrine/chromeos.c | 12 ++++++++++++ + 4 files changed, 59 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig +index c4c943e..6530242 100644 +--- a/src/mainboard/google/herobrine/Kconfig ++++ b/src/mainboard/google/herobrine/Kconfig +@@ -24,7 +24,8 @@ config BOARD_SPECIFIC_OPTIONS + select SPI_FLASH_WINBOND + select SPI_FLASH_MACRONIX + select MAINBOARD_HAS_CHROMEOS +- select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_SENOR ++ select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_GOOGLE_PIGLIN || BOARD_GOOGLE_HOGLIN ++ select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_HEROBRINE + select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_SENOR + + config VBOOT +@@ -51,4 +52,23 @@ config MAINBOARD_PART_NUMBER + default "Piglin" if BOARD_GOOGLE_PIGLIN + default "Hoglin" if BOARD_GOOGLE_HOGLIN + ++config DRIVER_TPM_I2C_BUS ++ depends on MAINBOARD_HAS_I2C_TPM_CR50 ++ hex ++ default 0xC ++ ++config DRIVER_TPM_I2C_ADDR ++ default 0x50 ++ ++config DRIVER_TPM_SPI_BUS ++ depends on MAINBOARD_HAS_SPI_TPM_CR50 ++ hex ++ default 0xE if BOARD_GOOGLE_PIGLIN || BOARD_GOOGLE_HOGLIN ++ default 0xC ++ ++config EC_GOOGLE_CHROMEEC_SPI_BUS ++ hex ++ default 0x8 if BOARD_GOOGLE_HEROBRINE ++ default 0xA if BOARD_GOOGLE_PIGLIN || BOARD_GOOGLE_HOGLIN ++ + endif # BOARD_GOOGLE_HEROBRINE_COMMON +diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h +index 367334a..012c659 100644 +--- a/src/mainboard/google/herobrine/board.h ++++ b/src/mainboard/google/herobrine/board.h +@@ -7,6 +7,21 @@ + #include <boardid.h> + #include <gpio.h> + ++ ++#if CONFIG(BOARD_GOOGLE_HEROBRINE) ++#define GPIO_EC_IN_RW GPIO(68) ++#define GPIO_AP_EC_INT GPIO(142) ++#define GPIO_H1_AP_INT GPIO(54) ++#elif CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) ++#define GPIO_EC_IN_RW GPIO(156) ++#define GPIO_AP_EC_INT GPIO(18) ++#define GPIO_H1_AP_INT GPIO(104) ++#elif CONFIG(BOARD_GOOGLE_SENOR) ++#define GPIO_EC_IN_RW dead_code_t(gpio_t) ++#define GPIO_AP_EC_INT dead_code_t(gpio_t) ++#define GPIO_H1_AP_INT dead_code_t(gpio_t) ++#endif ++ + #define GPIO_SD_CD_L GPIO(91) + + #if CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) +diff --git a/src/mainboard/google/herobrine/bootblock.c b/src/mainboard/google/herobrine/bootblock.c +index 05e53a6..c6e8765 100644 +--- a/src/mainboard/google/herobrine/bootblock.c ++++ b/src/mainboard/google/herobrine/bootblock.c +@@ -2,8 +2,19 @@ + + #include <bootblock_common.h> + #include "board.h" ++#include <soc/qupv3_i2c_common.h> ++#include <soc/qcom_qup_se.h> ++#include <soc/qupv3_spi_common.h> + + void bootblock_mainboard_init(void) + { + setup_chromeos_gpios(); ++ ++ if (CONFIG(BOARD_GOOGLE_HEROBRINE)) ++ i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */ ++ ++ if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN)) ++ qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz); /* H1/TPM SPI */ ++ ++ qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */ + } +diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c +index 9faf4ba..221519c 100644 +--- a/src/mainboard/google/herobrine/chromeos.c ++++ b/src/mainboard/google/herobrine/chromeos.c +@@ -3,9 +3,12 @@ + #include <boot/coreboot_tables.h> + #include <bootmode.h> + #include "board.h" ++#include <security/tpm/tis.h> + + void setup_chromeos_gpios(void) + { ++ gpio_input_pullup(GPIO_EC_IN_RW); ++ gpio_input_pullup(GPIO_AP_EC_INT); + gpio_input_pullup(GPIO_SD_CD_L); + + if (CONFIG(HEROBRINE_HAS_FINGERPRINT)) { +@@ -18,6 +21,10 @@ void setup_chromeos_gpios(void) + void fill_lb_gpios(struct lb_gpios *gpios) + { + struct lb_gpio chromeos_gpios[] = { ++ {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), ++ "EC in RW"}, ++ {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), ++ "EC interrupt"}, + {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), + "SD card detect"}, + }; +@@ -30,3 +37,8 @@ int get_ec_is_trusted(void) + /* Stub GPIO. */ + return 0; + } ++ ++int tis_plat_irq_status(void) ++{ ++ return gpio_irq_status(GPIO_H1_AP_INT); ++} +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0003-Herobrine-sc7280-Add-support-for-audio.patch b/0003-Herobrine-sc7280-Add-support-for-audio.patch new file mode 100644 index 0000000..b8b7796 --- /dev/null +++ b/0003-Herobrine-sc7280-Add-support-for-audio.patch @@ -0,0 +1,96 @@ +From 4544d38f7f5ba4c05acb5b7332070337409e3737 Mon Sep 17 00:00:00 2001 +From: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org> +Date: Fri, 27 Aug 2021 19:31:34 +0530 +Subject: [PATCH 03/17] Herobrine: sc7280: Add support for audio + +Add gpio configuration for target specific i2s ports + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 developement board + +Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org> +Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002 +--- + src/mainboard/google/herobrine/board.h | 11 +++++++++++ + src/mainboard/google/herobrine/chromeos.c | 3 +++ + src/mainboard/google/herobrine/mainboard.c | 14 ++++++++++++++ + 3 files changed, 28 insertions(+) + +diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h +index 012c659..68fc37e 100644 +--- a/src/mainboard/google/herobrine/board.h ++++ b/src/mainboard/google/herobrine/board.h +@@ -31,6 +31,17 @@ + #define USB_HUB_LDO_EN GPIO(24) + #endif + ++#if CONFIG(BOARD_GOOGLE_HEROBRINE) ++#define USB_HUB_LDO_EN GPIO(24) ++#elif CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) ++#define USB_HUB_LDO_EN GPIO(157) ++#endif ++ ++#define GPIO_AMP_ENABLE GPIO(63) ++#define GPIO106_MI2S1_SCK GPIO(106) ++#define GPIO107_MI2S1_DATA0 GPIO(107) ++#define GPIO108_MI2S1_WS GPIO(108) ++ + #define QCOM_SC7280_SKU1 0x0 + #define QCOM_SC7280_SKU2 0x1 + +diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c +index 221519c..a79e95a 100644 +--- a/src/mainboard/google/herobrine/chromeos.c ++++ b/src/mainboard/google/herobrine/chromeos.c +@@ -16,6 +16,7 @@ void setup_chromeos_gpios(void) + gpio_output(GPIO_FP_RST_L, 0); + gpio_output(GPIO_EN_FP_RAILS, 0); + } ++ gpio_output(GPIO_AMP_ENABLE, 0); + } + + void fill_lb_gpios(struct lb_gpios *gpios) +@@ -27,6 +28,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) + "EC interrupt"}, + {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), + "SD card detect"}, ++ {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), ++ "speaker enable"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c +index a2e0786..1f0901b 100644 +--- a/src/mainboard/google/herobrine/mainboard.c ++++ b/src/mainboard/google/herobrine/mainboard.c +@@ -38,6 +38,19 @@ static void configure_sdhci(void) + write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4); + } + ++static void qi2s_configure_gpios(void) ++{ ++ ++ gpio_configure(GPIO106_MI2S1_SCK, GPIO106_FUNC_MI2S1_SCK, ++ GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); ++ ++ gpio_configure(GPIO108_MI2S1_WS, GPIO108_FUNC_MI2S1_WS, ++ GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); ++ ++ gpio_configure(GPIO107_MI2S1_DATA0, GPIO107_FUNC_MI2S1_DATA0, ++ GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); ++} ++ + static void mainboard_init(struct device *dev) + { + /* Configure clock for eMMC */ +@@ -83,6 +96,7 @@ static void mainboard_init(struct device *dev) + gpio_output(GPIO_FP_RST_L, 1); + + setup_usb(); ++ qi2s_configure_gpios(); + } + + static void mainboard_enable(struct device *dev) +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0004-Herobrine-TPM-Config-Changes-to-support-audio.patch b/0004-Herobrine-TPM-Config-Changes-to-support-audio.patch new file mode 100644 index 0000000..732f06d --- /dev/null +++ b/0004-Herobrine-TPM-Config-Changes-to-support-audio.patch @@ -0,0 +1,40 @@ +From 30c3f61d883abbf515908004afb69a01f3c48241 Mon Sep 17 00:00:00 2001 +From: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org> +Date: Thu, 16 Dec 2021 07:45:46 +0530 +Subject: [PATCH 04/17] Herobrine: TPM Config Changes to support audio + +Add configuration for target specific i2s ports + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 developement board + +Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org> +Change-Id: Ifb3452faa2c43e2303ab4b1fef193184ffe4a938 +--- + src/mainboard/google/herobrine/chromeos.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c +index a79e95a..7d670c5 100644 +--- a/src/mainboard/google/herobrine/chromeos.c ++++ b/src/mainboard/google/herobrine/chromeos.c +@@ -16,6 +16,7 @@ void setup_chromeos_gpios(void) + gpio_output(GPIO_FP_RST_L, 0); + gpio_output(GPIO_EN_FP_RAILS, 0); + } ++ gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_output(GPIO_AMP_ENABLE, 0); + } + +@@ -28,6 +29,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) + "EC interrupt"}, + {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), + "SD card detect"}, ++ {GPIO_H1_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_H1_AP_INT), ++ "TPM interrupt"}, + {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), + "speaker enable"}, + }; +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0005-sc7280-enable-bl31-and-SDI-feature-support.patch b/0005-sc7280-enable-bl31-and-SDI-feature-support.patch new file mode 100644 index 0000000..f017946 --- /dev/null +++ b/0005-sc7280-enable-bl31-and-SDI-feature-support.patch @@ -0,0 +1,64 @@ +From e112bbdc93171f542946e748f47d1e01ced11a6e Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Tue, 24 Nov 2020 15:52:26 +0530 +Subject: [PATCH 05/17] sc7280: enable bl31 and SDI feature support + +Developer/Reviewer, be aware of this patch from Napali: +https://review.coreboot.org/c/coreboot/+/28014/44 + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 development board + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4 +--- + src/soc/qualcomm/sc7280/Kconfig | 1 + + src/soc/qualcomm/sc7280/Makefile.inc | 20 ++++++++++++++++++++ + 2 files changed, 21 insertions(+) + +diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig +index 24d5c20..68234f9 100644 +--- a/src/soc/qualcomm/sc7280/Kconfig ++++ b/src/soc/qualcomm/sc7280/Kconfig +@@ -6,6 +6,7 @@ config SOC_QUALCOMM_SC7280 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 ++ select ARM64_USE_ARM_TRUSTED_FIRMWARE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER +diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc +index 6a02bdb..4c83722 100644 +--- a/src/soc/qualcomm/sc7280/Makefile.inc ++++ b/src/soc/qualcomm/sc7280/Makefile.inc +@@ -51,6 +51,26 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + SC7280_BLOB := $(top)/3rdparty/qc_blobs/sc7280 + + ################################################################################ ++BL31_MAKEARGS += PLAT=sc7280 ++ ++ifeq ($(CONFIG_QC_SDI_ENABLE),y) ++BL31_MAKEARGS += QTI_SDI_BUILD=1 ++BL31_MAKEARGS += QTISECLIB_PATH=$(SC7280_BLOB)/qtiseclib/libqtisec_dbg.a ++else ++BL31_MAKEARGS += QTISECLIB_PATH=$(SC7280_BLOB)/qtiseclib/libqtisec.a ++endif # CONFIG_QC_SDI_ENABLE ++ ++################################################################################ ++ifeq ($(CONFIG_QC_SDI_ENABLE),y) ++QCSDI_FILE := $(SC7280_BLOB)/boot/QcSdi.elf ++QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi ++$(QCSDI_CBFS)-file := $(QCSDI_FILE) ++$(QCSDI_CBFS)-type := stage ++$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG) ++cbfs-files-y += $(QCSDI_CBFS) ++endif ++ ++################################################################################ + QC_SEC_FILE := $(SC7280_BLOB)/qc_sec/qc_sec.mbn + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf + @util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \ +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0006-sc7280-Add-Modem-region-in-memlayout-to-avoid-modem-.patch b/0006-sc7280-Add-Modem-region-in-memlayout-to-avoid-modem-.patch new file mode 100644 index 0000000..f7de5a0 --- /dev/null +++ b/0006-sc7280-Add-Modem-region-in-memlayout-to-avoid-modem-.patch @@ -0,0 +1,120 @@ +From cc2635fe0b510a561897d17afb0ee2f28ca36d1c Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Wed, 6 Oct 2021 14:19:56 +0530 +Subject: [PATCH 06/17] sc7280: Add Modem region in memlayout to avoid modem + cleanup in Secboot reboot. + +modem region to be handled in QC_SEC + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 +--- + .../qualcomm/common/include/soc/symbols_common.h | 1 + + src/soc/qualcomm/sc7280/Makefile.inc | 2 ++ + src/soc/qualcomm/sc7280/carve_out.c | 23 ++++++++++++++++++++++ + src/soc/qualcomm/sc7280/memlayout.ld | 1 + + src/soc/qualcomm/sc7280/soc.c | 9 ++++++++- + 5 files changed, 35 insertions(+), 1 deletion(-) + create mode 100644 src/soc/qualcomm/sc7280/carve_out.c + +diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h +index 7f3cfbb..7560266 100644 +--- a/src/soc/qualcomm/common/include/soc/symbols_common.h ++++ b/src/soc/qualcomm/common/include/soc/symbols_common.h +@@ -25,5 +25,6 @@ DECLARE_REGION(dram_wlan) + DECLARE_REGION(dram_wpss) + DECLARE_REGION(shrm) + DECLARE_REGION(dram_cpucp) ++DECLARE_REGION(dram_modem) + + #endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ +diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc +index 4c83722..85508e9 100644 +--- a/src/soc/qualcomm/sc7280/Makefile.inc ++++ b/src/soc/qualcomm/sc7280/Makefile.inc +@@ -31,10 +31,12 @@ romstage-y += ../common/qclib.c + romstage-y += ../common/mmu.c + romstage-y += mmu.c + romstage-y += ../common/usb/usb.c ++romstage-y += carve_out.c + romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c + + ################################################################################ + ramstage-y += soc.c ++ramstage-y += carve_out.c + ramstage-y += cbmem.c + ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c + ramstage-y += ../common/usb/usb.c +diff --git a/src/soc/qualcomm/sc7280/carve_out.c b/src/soc/qualcomm/sc7280/carve_out.c +new file mode 100644 +index 0000000..66192fc +--- /dev/null ++++ b/src/soc/qualcomm/sc7280/carve_out.c +@@ -0,0 +1,23 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include <arch/stages.h> ++#include <soc/mmu_common.h> ++#include <soc/symbols_common.h> ++#include <device/mmio.h> ++#include <console/console.h> ++ ++#define MODEM_ONLY 0x004c5445 ++ ++bool soc_modem_carve_out(void **start, void **end) ++{ ++ uint32_t modem_id = read32(_modem_id); ++ ++ switch (modem_id) { ++ case MODEM_ONLY: ++ *start = _dram_modem; ++ *end = _edram_modem; ++ return true; ++ default: ++ return false; ++ } ++} +diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld +index 57cdb59..1677dc4 100644 +--- a/src/soc/qualcomm/sc7280/memlayout.ld ++++ b/src/soc/qualcomm/sc7280/memlayout.ld +@@ -56,6 +56,7 @@ SECTIONS + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + REGION(dram_cpucp,0x80B00000, 0x100000, 0x1000) + REGION(dram_wlan, 0x80C00000, 0xC00000, 0x1000) ++ REGION(dram_modem, 0x8B800000, 0xF600000, 0x1000) + REGION(dram_wpss, 0x9AE00000, 0x1900000, 0x1000) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c +index 8d27a46..0447833 100644 +--- a/src/soc/qualcomm/sc7280/soc.c ++++ b/src/soc/qualcomm/sc7280/soc.c +@@ -6,9 +6,12 @@ + #include <soc/symbols_common.h> + #include <soc/aop_common.h> + #include <soc/cpucp.h> +- ++#include <console/console.h> + static void soc_read_resources(struct device *dev) + { ++ void *start = NULL; ++ void *end = NULL; ++ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, +@@ -21,6 +24,10 @@ static void soc_read_resources(struct device *dev) + REGION_SIZE(dram_aop) / KiB); + reserved_ram_resource(dev, 5, (uintptr_t)_dram_cpucp / KiB, + REGION_SIZE(dram_cpucp) / KiB); ++ if (soc_modem_carve_out(&start, &end)) ++ { ++ reserved_ram_resource(dev, 6, (uintptr_t)start / KiB, (end - start) / KiB); ++ } + } + + static void soc_init(struct device *dev) +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0007-sc7180-Update-video-mode-active-horizontal-vertical-.patch b/0007-sc7180-Update-video-mode-active-horizontal-vertical-.patch new file mode 100644 index 0000000..2e333bd --- /dev/null +++ b/0007-sc7180-Update-video-mode-active-horizontal-vertical-.patch @@ -0,0 +1,60 @@ +From 2eb7c25bd21a6b87524a1417fb568cc28cecb789 Mon Sep 17 00:00:00 2001 +From: Vinod Polimera <vpolimer(a)codeaurora.org> +Date: Wed, 29 Sep 2021 10:23:28 +0530 +Subject: [PATCH 07/17] sc7180: Update video mode active + horizontal/vertical/total calculations + +Remove vbp & hbp as the names are misleading and use edid variables +to simplify the video mode active and total calculations. + +Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be +Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> +--- + src/soc/qualcomm/sc7180/display/dsi.c | 19 ++++++------------- + 1 file changed, 6 insertions(+), 13 deletions(-) + +diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c +index 15d36ed..48dc2b3 100644 +--- a/src/soc/qualcomm/sc7180/display/dsi.c ++++ b/src/soc/qualcomm/sc7180/display/dsi.c +@@ -100,7 +100,6 @@ void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp) + { + uint16_t dst_format; + uint8_t lane_en = 15; /* Enable 4 lanes by default */ +- uint16_t hfp, hbp, vfp, vbp; + + switch (bpp) { + case 16: +@@ -115,23 +114,17 @@ void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp) + break; + } + +- hfp = edid->mode.hso; +- hbp = edid->mode.hbl - edid->mode.hso; +- vfp = edid->mode.vso; +- vbp = edid->mode.vbl - edid->mode.vso; +- + write32(&dsi0->video_mode_active_h, +- ((edid->mode.ha + hbp) << 16) | +- hbp); ++ ((edid->mode.ha + edid->mode.hbl - edid->mode.hso) << 16) | ++ (edid->mode.hbl - edid->mode.hso)); + + write32(&dsi0->video_mode_active_v, +- ((edid->mode.va + vbp) << 16) | (vbp)); ++ ((edid->mode.va + edid->mode.vbl - edid->mode.vso) << 16) | ++ (edid->mode.vbl - edid->mode.vso)); + + write32(&dsi0->video_mode_active_total, +- ((edid->mode.va + vfp + +- vbp - 1) << 16) | +- (edid->mode.ha + hfp + +- hbp - 1)); ++ ((edid->mode.va + edid->mode.vbl - 1) << 16) | ++ (edid->mode.ha + edid->mode.hbl - 1)); + + write32(&dsi0->video_mode_active_hsync, (edid->mode.hspw << 16)); + write32(&dsi0->video_mode_active_vsync, 0x0); +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0008-src-mainboard-herobrine-Add-support-QUP-FW-for-I2C-a.patch b/0008-src-mainboard-herobrine-Add-support-QUP-FW-for-I2C-a.patch new file mode 100644 index 0000000..9cce32a --- /dev/null +++ b/0008-src-mainboard-herobrine-Add-support-QUP-FW-for-I2C-a.patch @@ -0,0 +1,43 @@ +From 7a6f107e95261095b9b02497c704fcbf49f532e4 Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Fri, 5 Nov 2021 17:27:46 +0530 +Subject: [PATCH 08/17] src/mainboard/herobrine: Add support QUP FW for I2C and + SPI + +Loading QUP FW for hoglin and senor configuration for I2C, SPI and UART. + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 development board. + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: I08b1d38fef84ef341809a901e2287f70ca5a0314 + +src/mainboard/herobrine: Add support for senor QUP FW for I2C and SPI + +Loading QUP FW for senor configuration for I2C, SPI and UART. +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 development board. + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: I6fdd09bb437547e6d12eb60c4b2917d2a3074618 +--- + src/mainboard/google/herobrine/mainboard.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c +index 1f0901b..1960e69 100644 +--- a/src/mainboard/google/herobrine/mainboard.c ++++ b/src/mainboard/google/herobrine/mainboard.c +@@ -81,7 +81,8 @@ static void mainboard_init(struct device *dev) + qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); + /* Fingerprint SPI */ + qupv3_se_fw_load_and_init(QUPV3_1_SE3, SE_PROTOCOL_SPI, MIXED); +- } else if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN)) { ++ } else if (CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) || ++ CONFIG(BOARD_GOOGLE_HOGLIN)) { + /* APPS I2C */ + qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, GSI); + /* ESIM SPI */ +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0009-libpayload-Parse-DDR-Information-through-coreboot-ta.patch b/0009-libpayload-Parse-DDR-Information-through-coreboot-ta.patch new file mode 100644 index 0000000..7d88fa0 --- /dev/null +++ b/0009-libpayload-Parse-DDR-Information-through-coreboot-ta.patch @@ -0,0 +1,157 @@ +From b0193a50324a1144a445da84e33c2a570a663dc0 Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Wed, 10 Nov 2021 05:22:47 +0530 +Subject: [PATCH 09/17] libpayload: Parse DDR Information through coreboot + tables + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 developement board + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e +--- + payloads/libpayload/include/coreboot_tables.h | 1 + + payloads/libpayload/include/libpayload.h | 1 + + payloads/libpayload/include/mem_chip_info.h | 46 +++++++++++++++++++++++++++ + payloads/libpayload/include/sysinfo.h | 1 + + payloads/libpayload/libc/coreboot.c | 28 ++++++++++++++++ + 5 files changed, 77 insertions(+) + create mode 100644 payloads/libpayload/include/mem_chip_info.h + +diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h +index 3fd3fc8..e211805 100644 +--- a/payloads/libpayload/include/coreboot_tables.h ++++ b/payloads/libpayload/include/coreboot_tables.h +@@ -88,6 +88,7 @@ enum { + CB_TAG_OPTION_ENUM = 0x00ca, + CB_TAG_OPTION_DEFAULTS = 0x00cb, + CB_TAG_OPTION_CHECKSUM = 0x00cc, ++ CB_TAG_MEM_CHIP_INFO = 0x00ce, /* memchip info */ + }; + + struct cbuint64 { +diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h +index 3895710..a318d16 100644 +--- a/payloads/libpayload/include/libpayload.h ++++ b/payloads/libpayload/include/libpayload.h +@@ -64,6 +64,7 @@ + #include <sysinfo.h> + #include <pci.h> + #include <archive.h> ++#include <mem_chip_info.h> + + /* Double-evaluation unsafe min/max, for bitfields and outside of functions */ + #define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) +diff --git a/payloads/libpayload/include/mem_chip_info.h b/payloads/libpayload/include/mem_chip_info.h +new file mode 100644 +index 0000000..508177f +--- /dev/null ++++ b/payloads/libpayload/include/mem_chip_info.h +@@ -0,0 +1,46 @@ ++/* ++ * ++ * Copyright (C) 2008 Advanced Micro Devices, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#ifndef _MEM_CHIP_INFO_H ++#define _MEM_CHIP_INFO_H ++ ++typedef struct { ++ uint8_t type; ++ uint8_t num_channels; ++ uint8_t reserved[6]; ++ struct { ++ uint64_t density; ++ uint8_t io_width; ++ uint8_t manufacturer_id; ++ uint8_t revision_id[2]; ++ uint8_t reserved[4]; ++ uint8_t serial_id[8]; // for potential future LPDDR5 expansion ++ } channel[2]; ++}dram_info; ++ ++#endif +diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h +index 376f298..eba4b89 100644 +--- a/payloads/libpayload/include/sysinfo.h ++++ b/payloads/libpayload/include/sysinfo.h +@@ -83,6 +83,7 @@ struct sysinfo_t { + uintptr_t compiler; + uintptr_t linker; + uintptr_t assembler; ++ uintptr_t mem_chip_base; + + uintptr_t cb_version; + +diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c +index 79a382b..6f4f4a4 100644 +--- a/payloads/libpayload/libc/coreboot.c ++++ b/payloads/libpayload/libc/coreboot.c +@@ -118,6 +118,31 @@ static void cb_parse_mac_addresses(unsigned char *ptr, + info->macs[i] = macs->mac_addrs[i]; + } + ++static void cb_parse_mem_chip_info(void *ptr, struct sysinfo_t *info) ++{ ++ info->mem_chip_base = get_cbmem_addr(ptr); ++} ++ ++static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) ++{ ++ info->tstamp_table = get_cbmem_addr(ptr); ++} ++ ++static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) ++{ ++ info->cbmem_cons = get_cbmem_addr(ptr); ++} ++ ++static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) ++{ ++ info->acpi_gnvs = get_cbmem_addr(ptr); ++} ++ ++static void cb_parse_acpi_cnvs(unsigned char *ptr, struct sysinfo_t *info) ++{ ++ info->acpi_cnvs = get_cbmem_addr(ptr); ++} ++ + static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info) + { + struct cb_board_config *const config = (struct cb_board_config *)ptr; +@@ -349,6 +374,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) + case CB_TAG_ASSEMBLER: + cb_parse_string(ptr, &info->assembler); + break; ++ case CB_TAG_MEM_CHIP_INFO: ++ cb_parse_mem_chip_info(ptr, info); ++ break; + #if CONFIG(LP_NVRAM) + case CB_TAG_CMOS_OPTION_TABLE: + cb_parse_optiontable(ptr, info); +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0010-src-lib-Added-CBMEM-tag-id-to-parse-ddr-information.patch b/0010-src-lib-Added-CBMEM-tag-id-to-parse-ddr-information.patch new file mode 100644 index 0000000..358ddbc --- /dev/null +++ b/0010-src-lib-Added-CBMEM-tag-id-to-parse-ddr-information.patch @@ -0,0 +1,64 @@ +From 64897d1e299a904b8867c3f97f975898f63f8008 Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Wed, 10 Nov 2021 05:23:25 +0530 +Subject: [PATCH 10/17] src/lib: Added CBMEM tag id to parse ddr information + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 developement board + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f +--- + src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 5 ++++- + src/commonlib/include/commonlib/coreboot_tables.h | 1 + + src/lib/coreboot_table.c | 1 + + 3 files changed, 6 insertions(+), 1 deletion(-) + +diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +index 4c13535..9a87b3d 100644 +--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h ++++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +@@ -79,6 +79,7 @@ + #define CBMEM_ID_FSP_LOGO 0x4c4f474f + #define CBMEM_ID_SMM_COMBUFFER 0x53534d32 + #define CBMEM_ID_TYPE_C_INFO 0x54595045 ++#define CBMEM_ID_MEM_CHIP_INFO 0x10 + + #define CBMEM_ID_TO_NAME_TABLE \ + { CBMEM_ID_ACPI, "ACPI " }, \ +@@ -152,5 +153,7 @@ + { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ + { CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \ + { CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \ +- { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"} ++ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ ++ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}, \ ++ { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO "} + #endif /* _CBMEM_ID_H_ */ +diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h +index 91da8e0..c47b2f6 100644 +--- a/src/commonlib/include/commonlib/coreboot_tables.h ++++ b/src/commonlib/include/commonlib/coreboot_tables.h +@@ -91,6 +91,7 @@ enum { + LB_TAG_OPTION_ENUM = 0x00ca, + LB_TAG_OPTION_DEFAULTS = 0x00cb, + LB_TAG_OPTION_CHECKSUM = 0x00cc, ++ LB_TAG_MEM_CHIP_INFO = 0x00ce, /* memchip info */ + }; + + /* Since coreboot is usually compiled 32bit, gcc will align 64bit +diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c +index d0cba80..ccb2320 100644 +--- a/src/lib/coreboot_table.c ++++ b/src/lib/coreboot_table.c +@@ -253,6 +253,7 @@ static void add_cbmem_pointers(struct lb_header *header) + {CBMEM_ID_FMAP, LB_TAG_FMAP}, + {CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF}, + {CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO}, ++ {CBMEM_ID_MEM_CHIP_INFO, LB_TAG_MEM_CHIP_INFO} + }; + int i; + +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0011-soc-Added-dram-information-to-cbmem.patch b/0011-soc-Added-dram-information-to-cbmem.patch new file mode 100644 index 0000000..44f87a3 --- /dev/null +++ b/0011-soc-Added-dram-information-to-cbmem.patch @@ -0,0 +1,89 @@ +From eb4d439e8ccd11c518e052bb317d4d5ccd10d626 Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Wed, 10 Nov 2021 05:24:17 +0530 +Subject: [PATCH 11/17] soc: Added dram information to cbmem + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 developement board + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 +--- + src/soc/qualcomm/common/include/soc/qclib_common.h | 1 + + src/soc/qualcomm/common/qclib.c | 34 ++++++++++++++++++++++ + 2 files changed, 35 insertions(+) + +diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h +index c906ef2..648b29d 100644 +--- a/src/soc/qualcomm/common/include/soc/qclib_common.h ++++ b/src/soc/qualcomm/common/include/soc/qclib_common.h +@@ -22,6 +22,7 @@ + #define QCLIB_TE_DDR_TRAINING_DATA "ddr_training_data" + #define QCLIB_TE_LIMITS_CFG_DATA "limits_cfg_data" + #define QCLIB_TE_QCSDI "qcsdi" ++#define QCLIB_TE_MEM_CHIP_INFO "mem_chip_info" + + /* BA_BMASK_VALUES (blob_attributes bit mask values) */ + #define QCLIB_BA_SAVE_TO_STORAGE 0x00000001 +diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c +index e016f25..85821fd 100644 +--- a/src/soc/qualcomm/common/qclib.c ++++ b/src/soc/qualcomm/common/qclib.c +@@ -19,6 +19,32 @@ + + #define QCLIB_VERSION 0 + ++/* store QcLib return data until ROMSTAGE_CBMEM_INIT_HOOK runs */ ++static void *mem_chip_info; ++static uint32_t mem_chip_size; ++ ++static void write_mem_chip_information(struct qclib_cb_if_table_entry *te); ++static void write_mem_chip_information(struct qclib_cb_if_table_entry *te) ++{ ++ /* Save mem_chip_info in local variables ahead of hook running */ ++ mem_chip_info = (void *)te->blob_address; ++ mem_chip_size = te->size; ++} ++ ++static void add_mem_chip_info(int unused) ++{ ++ void *mem_region_base; ++ ++ /* Add cbmem */ ++ mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); ++ ASSERT(mem_region_base != NULL); ++ ++ /* Migrate the data into CBMEM */ ++ memcpy(mem_region_base, mem_chip_info, mem_chip_size); ++} ++ ++ROMSTAGE_CBMEM_INIT_HOOK(add_mem_chip_info); ++ + struct qclib_cb_if_table qclib_cb_if_table = { + .magic = QCLIB_MAGIC_NUMBER, + .version = QCLIB_INTERFACE_VERSION, +@@ -87,6 +113,10 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te) + + write_qclib_log_to_cbmemc(te); + ++ } else if (!strncmp(QCLIB_TE_MEM_CHIP_INFO, te->name, ++ sizeof(te->name))) { ++ write_mem_chip_information(te); ++ + } else { + + printk(BIOS_WARNING, "%s write not implemented\n", te->name); +@@ -139,6 +169,10 @@ void qclib_load_and_run(void) + qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, + _ddr_training, REGION_SIZE(ddr_training), 0); + ++ /* Attempt to read MEM CHIP information */ ++ qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, ++ mem_chip_info, sizeof(mem_chip_info), 0); ++ + /* Attempt to load PMICCFG Blob */ + data_size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic)); +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0012-HACK-Senor-build-support-HACK.patch b/0012-HACK-Senor-build-support-HACK.patch new file mode 100644 index 0000000..63fe68c --- /dev/null +++ b/0012-HACK-Senor-build-support-HACK.patch @@ -0,0 +1,45 @@ +From 35906d9ed644ad09ecaf257c3e0d436d0849821c Mon Sep 17 00:00:00 2001 +From: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Date: Tue, 9 Nov 2021 00:20:56 +0530 +Subject: [PATCH 12/17] HACK: Senor build support HACK + +Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> +Change-Id: Iefa6e598af83ad0be0139afe6c4050b868aba614 +--- + src/mainboard/google/herobrine/board.h | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h +index 68fc37e..0a35274 100644 +--- a/src/mainboard/google/herobrine/board.h ++++ b/src/mainboard/google/herobrine/board.h +@@ -12,14 +12,11 @@ + #define GPIO_EC_IN_RW GPIO(68) + #define GPIO_AP_EC_INT GPIO(142) + #define GPIO_H1_AP_INT GPIO(54) +-#elif CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) ++#elif CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) \ ++ || CONFIG(BOARD_GOOGLE_HOGLIN) + #define GPIO_EC_IN_RW GPIO(156) + #define GPIO_AP_EC_INT GPIO(18) + #define GPIO_H1_AP_INT GPIO(104) +-#elif CONFIG(BOARD_GOOGLE_SENOR) +-#define GPIO_EC_IN_RW dead_code_t(gpio_t) +-#define GPIO_AP_EC_INT dead_code_t(gpio_t) +-#define GPIO_H1_AP_INT dead_code_t(gpio_t) + #endif + + #define GPIO_SD_CD_L GPIO(91) +@@ -33,7 +30,8 @@ + + #if CONFIG(BOARD_GOOGLE_HEROBRINE) + #define USB_HUB_LDO_EN GPIO(24) +-#elif CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) ++#elif CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) \ ++ || CONFIG(BOARD_GOOGLE_HOGLIN) + #define USB_HUB_LDO_EN GPIO(157) + #endif + +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0013-HACK-sc7280-QSIP-SPI-NOR-addressing-mode-for-SKU1-an.patch b/0013-HACK-sc7280-QSIP-SPI-NOR-addressing-mode-for-SKU1-an.patch new file mode 100644 index 0000000..bf94cdb --- /dev/null +++ b/0013-HACK-sc7280-QSIP-SPI-NOR-addressing-mode-for-SKU1-an.patch @@ -0,0 +1,89 @@ +From b04d800f461af5149e4ed14d5c45a7d77f2ecde6 Mon Sep 17 00:00:00 2001 +From: Veerabhadrarao Badiganti <vbadigan(a)codeaurora.org> +Date: Thu, 28 Jan 2021 14:58:25 +0530 +Subject: [PATCH 13/17] HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and + SKU2 HACK + +Change Addressing mode of SPI nor from 4-bytes to 3-bytes As 4-bytes not +supporting in coreboot. + +BUG=b:182963902 +TEST=Validated on qualcomm sc7280 developement board + +Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 +Signed-off-by: Veerabhadrarao Badiganti <vbadigan(a)codeaurora.org> +Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> +--- + src/drivers/spi/spi_flash.c | 42 ++++++++++++++++++++++++++++++++++ + src/mainboard/google/herobrine/Kconfig | 2 ++ + 2 files changed, 44 insertions(+) + +diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c +index f3cecd5..92c2193 100644 +--- a/src/drivers/spi/spi_flash.c ++++ b/src/drivers/spi/spi_flash.c +@@ -515,6 +515,48 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash) + " CONFIG_ROM_SIZE 0x%x!!\n", flash->size, + CONFIG_ROM_SIZE); + } ++ ++#if CONFIG(SPI_FLASH_MACRONIX_MODE) ++ if (flash->vendor == VENDOR_ID_MACRONIX) { ++ u8 reg8; ++ spi_flash_cmd(&flash->spi, 0x15, &reg8, sizeof(reg8)); ++ if (reg8 & 0x20) ++ printk(BIOS_WARNING, ++ "4 byte addr mode set:%02x\n.Falling back to 3 byte addr mode\n", ++ reg8); ++ spi_flash_cmd(&flash->spi, 0xe9, NULL, 0); ++ spi_flash_cmd(&flash->spi, 0x15, &reg8, sizeof(reg8)); ++ if (reg8 & 0x20) { ++ printk(BIOS_WARNING, ++ "4 byte addr mode set:%02x\n.Exiting 4 byte mode not working. Looping here\n", ++ reg8); ++ while (1) ++ ; ++ } ++ } ++#endif ++ ++#if CONFIG(SPI_FLASH_WINBOND_MODE) ++ if (flash->vendor == VENDOR_ID_WINBOND) { ++ u8 reg8; ++ /*Check addressing mode*/ ++ spi_flash_cmd(&flash->spi, 0x15, &reg8, sizeof(reg8)); ++ if (reg8 & 0x1) ++ printk(BIOS_WARNING, ++ "4 byte addr mode set:%02x\n.Falling back to 3 byte addr mode\n", ++ reg8); ++ spi_flash_cmd(&flash->spi, 0xe9, NULL, 0); ++ spi_flash_cmd(&flash->spi, 0x15, &reg8, sizeof(reg8)); ++ if (reg8 & 0x1) { ++ printk(BIOS_WARNING, ++ "4 byte addr mode set:%02x\n.Exiting 4 byte mode not working. Looping here\n" ++ reg8); ++ while (1) ++ ; ++ } ++ } ++#endif ++ + return 0; + } + +diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig +index 6530242..47ef939 100644 +--- a/src/mainboard/google/herobrine/Kconfig ++++ b/src/mainboard/google/herobrine/Kconfig +@@ -22,6 +22,8 @@ config BOARD_SPECIFIC_OPTIONS + select SOC_QUALCOMM_SC7280 + select SPI_FLASH + select SPI_FLASH_WINBOND ++ select SPI_FLASH_WINBOND_MODE ++ select SPI_FLASH_MACRONIX_MODE + select SPI_FLASH_MACRONIX + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_GOOGLE_PIGLIN || BOARD_GOOGLE_HOGLIN +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0014-HACK-Herobrine-Reinit-TPM-INT-GPIO.patch b/0014-HACK-Herobrine-Reinit-TPM-INT-GPIO.patch new file mode 100644 index 0000000..b54be1f --- /dev/null +++ b/0014-HACK-Herobrine-Reinit-TPM-INT-GPIO.patch @@ -0,0 +1,62 @@ +From 70d3cecfc0ef65ad7fe7866d1966576f392e71cb Mon Sep 17 00:00:00 2001 +From: Shelley Chen <shchen(a)google.com> +Date: Wed, 18 Aug 2021 01:21:37 -0700 +Subject: [PATCH 14/17] HACK: Herobrine: Reinit TPM INT GPIO + +We noticed at some point after running the blobs that we started +getting TPM communication errors and realized that some QC blob was +reconfiguring this GPIO during execution. We haven't debugged to +which blob actually does this, so basically reinitializing the TPM +interrupt GPIO excessively to get around this issue for now. + +Signed-off-by: Shelley Chen <shchen(a)google.com> +Change-Id: I30426cc0392a640fb6d3b1d0fafca7e9a67a76c3 +--- + src/mainboard/google/herobrine/boardid.c | 2 ++ + src/mainboard/google/herobrine/chromeos.c | 9 +++++++++ + 2 files changed, 11 insertions(+) + +diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c +index a8ff3bf..a09919c 100644 +--- a/src/mainboard/google/herobrine/boardid.c ++++ b/src/mainboard/google/herobrine/boardid.c +@@ -6,6 +6,8 @@ + #include <commonlib/bsd/cb_err.h> + #include <console/console.h> + #include <gpio.h> ++#include <security/tpm/tis.h> ++ + + uint32_t board_id(void) + { +diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c +index 7d670c5..a6bb8b7 100644 +--- a/src/mainboard/google/herobrine/chromeos.c ++++ b/src/mainboard/google/herobrine/chromeos.c +@@ -4,6 +4,7 @@ + #include <bootmode.h> + #include "board.h" + #include <security/tpm/tis.h> ++#include <soc/qupv3_i2c_common.h> + + void setup_chromeos_gpios(void) + { +@@ -44,7 +45,15 @@ int get_ec_is_trusted(void) + return 0; + } + ++void mainboard_blob_fix(void); + int tis_plat_irq_status(void) + { ++ mainboard_blob_fix(); + return gpio_irq_status(GPIO_H1_AP_INT); + } ++ ++void mainboard_blob_fix(void) ++{ ++ gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); ++ i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */ ++} +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0015-HACK-Herobrine-Reinit-TPM-INT-gpio-after-qclib-execu.patch b/0015-HACK-Herobrine-Reinit-TPM-INT-gpio-after-qclib-execu.patch new file mode 100644 index 0000000..786c7cd --- /dev/null +++ b/0015-HACK-Herobrine-Reinit-TPM-INT-gpio-after-qclib-execu.patch @@ -0,0 +1,37 @@ +From 4e51da24f299181bee21737687f39b8d7cb4a00c Mon Sep 17 00:00:00 2001 +From: Shelley Chen <shchen(a)google.com> +Date: Wed, 18 Aug 2021 01:27:47 -0700 +Subject: [PATCH 15/17] HACK: Herobrine: Reinit TPM INT gpio after qclib + executes + +Signed-off-by: Shelley Chen <shchen(a)google.com> +Change-Id: I4c43d120ebb49800c82aec263ff8c215b60c5201 +--- + src/soc/qualcomm/common/qclib.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c +index 85821fd..597d46b 100644 +--- a/src/soc/qualcomm/common/qclib.c ++++ b/src/soc/qualcomm/common/qclib.c +@@ -141,6 +141,7 @@ static void dump_te_table(void) + + __weak int qclib_soc_blob_load(void) { return 0; } + ++void mainboard_blob_fix(void); + void qclib_load_and_run(void) + { + int i; +@@ -249,6 +250,9 @@ void qclib_load_and_run(void) + mmu_disable(); + mmu_restore_context(&pre_qclib_mmu_context); + mmu_enable(); ++#if CONFIG(BOARD_GOOGLE_HEROBRINE) ++ mainboard_blob_fix(); ++#endif + + /* step through I/F table, handling return values */ + for (i = 0; i < qclib_cb_if_table.num_entries; i++) +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0016-HACK-herobrine-T32-scripts-working-in-standalone-env.patch b/0016-HACK-herobrine-T32-scripts-working-in-standalone-env.patch new file mode 100644 index 0000000..6d4872d --- /dev/null +++ b/0016-HACK-herobrine-T32-scripts-working-in-standalone-env.patch @@ -0,0 +1,156 @@ +From fcee352feca1af13380c8c5231a46e381d195834 Mon Sep 17 00:00:00 2001 +From: T Michael Turney <mturney(a)codeaurora.org> +Date: Fri, 6 Nov 2020 17:01:29 -0800 +Subject: [PATCH 16/17] HACK herobrine T32 scripts working in standalone + environment HACK + +Change-Id: I451344d887c7b6c0983594e4dea4ca2b030d65f1 +--- + util/qualcomm/scripts/cmm/debug_cb_common.cmm | 5 + + util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm | 118 +++++++++++++++++++++++ + 2 files changed, 123 insertions(+) + create mode 100644 util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm + +diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm +index cbcb004..a722864 100644 +--- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm ++++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm +@@ -126,6 +126,11 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName + else + d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode + ++ print "Hacking DDR ranges..." ++ B::D.S MD:0x1485B000 %LE %Long 0x80000000 ++ B::D.S MD:0x1485B004 %LE %Long 0 ++ B::D.S MD:0x1485B008 %LE %Long 0x80000000 ++ + print %String "Now the control is in ROMStage, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter +diff --git a/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm b/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm +new file mode 100644 +index 0000000..1337ddd +--- /dev/null ++++ b/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm +@@ -0,0 +1,118 @@ ++;============================================================================ ++;## SPDX-License-Identifier: GPL-2.0-only ++;============================================================================ ++; Name: ++; debug_cb_trogdor.cmm ++; ++; Description: ++; Debug coreboot trogdor front-end ++;============================================================================ ++ ++;============================================================================ ++; CMM script variables ++;============================================================================ ++ ++LOCAL &TargetPkg ++ ++GLOBAL &BBEntryAddr // Bootblock Entry ++GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec ++GLOBAL &VEREntryAddr // Verstage Entry ++GLOBAL &ROMEntryAddr // Romstage Entry ++GLOBAL &QCLEntryAddr // QCLstage Entry ++GLOBAL &RAMEntryAddr // Ramstage Entry ++GLOBAL &BL31EntryAddr // BL31 Entry ++GLOBAL &DCEntryAddr // Depthcharge Entry ++ ++GLOBAL &PreRamConsoleAddr ++GLOBAL &RamConsoleAddr ++GLOBAL &PreRamCbfsCache ++GLOBAL &VBoot2Work ++GLOBAL &Stack ++GLOBAL &Ttb ++GLOBAL &Timestamp ++GLOBAL &CbmemTop ++GLOBAL &PostRamCbfsCache ++ ++GLOBAL &CBTablePtr ++ ++;============================================================================ ++ ++;--------------------------------------------------- ++; Entry point ++;--------------------------------------------------- ++ENTRY &ImageName &RegAddress ++ ++ // Later these can be parameterized ++ &TargetPkg="herobrinePkg" ++ ++ // These settings come from .../src/soc/qualcomm/sc7280/memlayout.ld ++ &BBEntryAddr=0x14819000 ++ &VEREntryAddr=0x14680000 ++ &ROMEntryAddr=0x14680000 ++ &QCLEntryAddr=0x1486c950 ++ &RAMEntryAddr=0xA0800000 ++ &BL31EntryAddr=0xC0000000 ++ &DCEntryAddr=0xF1000000 ++ &KernelEntryAddr=0xD0000000 ++ ++ &PreRamConsoleAddr=0x14834800 ++ &VBoot2Work=0x1484F000 ++ &Stack=0x1484B000 ++ &Ttb=0x1483D000 ++ &Timestamp=0x1483C800 ++ &PreRamCbfsCache=0x14823000 ++ &CbmemTop=0x280000000 ++ &PostRamCbfsCache=0x9F800000 ++ // End of memlayout.ld settings ++ ++ // Common commands irrespective of &Mode ++ PATH ++ &CwDir=os.pwd() ++ PATH + &CwDir ++ ++ // position at top of coreboot tree ++ // find depth count for source loading ++ cd ..\..\..\.. ++ &srcpath=os.pwd() ++ ++ ++;--------------------------------------------------- ++; Setup area and log ++;--------------------------------------------------- ++ area.clear ++ area.reset ++ area.create CB_Logs 1000. 8192. ++ area.select CB_Logs ++ ++ area.view CB_Logs ++ ++ PRINT %String "Source Path: &srcpath" ++ ++ symbol.sourcepath.setbasedir &srcpath\src ++ ++ // Make parsing simple, upper-case parameters ++ &ImageName=STRING.UPR("&ImageName") ++ if (STR.CP("&ImageName","0X*")) ++ ( ++ &RegAddress=&ImageName ++ &ImageName="" ++ ) ++ &RegAddress=STRING.UPR("&RegAddress") ++ ++ PRINT %String "ImageName: &ImageName" ++ PRINT %String "RegAddress: &RegAddress" ++ ++ ;sys.d ++ ;sys.up ++ b.d ++ y.reset ++ ++ if (STR.CP("&RegAddress","0X*")) ++ D.S EZAXI:&RegAddress %LE %Long 0x80000000 ++ ++ go &BBEntryAddr ++ wait !run() ++ ++ DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName ++ ++ enddo +-- +Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation. + diff --git a/0017-HACK-trogdor-optimize-coreboot.rom-for-T32-flash-scr.patch b/0017-HACK-trogdor-optimize-coreboot.rom-for-T32-flash-scr.patch new file mode 100644 index 0000000..02ab552 --- /dev/null +++ b/0017-HACK-trogdor-optimize-coreboot.rom-for-T32-flash-scr.patch @@ -0,0 +1,97 @@ +From 8299191536984ce594fc2290f59081d2ac3d832e Mon Sep 17 00:00:00 2001 +From: T Michael Turney <mturney(a)codeaurora.org> +Date: Wed, 23 Oct 2019 13:57:31 -0700 +Subject: [PATCH 17/17] HACK trogdor: optimize coreboot.rom for T32 flash + script HACK + +Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 +Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> +--- + src/security/vboot/Makefile.inc | 2 ++ + util/qualcomm/optimize_coreboot | Bin 0 -> 8872 bytes + 2 files changed, 2 insertions(+) + create mode 100755 util/qualcomm/optimize_coreboot + +diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc +index d604d1c..febf658 100644 +--- a/src/security/vboot/Makefile.inc ++++ b/src/security/vboot/Makefile.inc +@@ -321,6 +321,8 @@ files_added:: $(obj)/VBLOCK_A.bin $(obj)/VBLOCK_B.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_A -f $(obj)/VBLOCK_A.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_B -f $(obj)/VBLOCK_B.bin + @printf " FLASHMAP Layout generated for RO, A and B partition.\n" ++ @printf "This compresses coreboot.rom for T32 Flash Script\n" ++ ./util/qualcomm/optimize_coreboot $(obj)/coreboot.rom $(obj)/coreboot_opt.rom + else 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Gerrit-MessageType: newchange

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Change in coreboot[master]: google/herobrine: configure gpio to detect board ID.
by build bot (Jenkins) (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Shelley Chen, Ravi kumar, Ravi Kumar Bokka. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56642 ) Change subject: google/herobrine: configure gpio to detect board ID. ...................................................................... Patch Set 36: (12 comments) File src/mainboard/google/herobrine/boardid.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/ca437099_ed75667b PS36, Line 14: if (CONFIG(BOARD_GOOGLE_HEROBRINE)){ space required before the open brace '{' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/79dad090_2f146c2f PS36, Line 19: else if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) || CONFIG(BOARD_GOOGLE_SENOR)){ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/60f9ad8c_809f7788 PS36, Line 19: else if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) || CONFIG(BOARD_GOOGLE_SENOR)){ space required before the open brace '{' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/6aadcf4c_0dbd8328 PS36, Line 19: else if (CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN) || CONFIG(BOARD_GOOGLE_SENOR)){ else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/15fb82e6_814b52c9 PS36, Line 20: pins[2] = GPIO(50); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/5b37bdec_7d664b62 PS36, Line 20: pins[2] = GPIO(50); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/681787a5_18b045be PS36, Line 21: pins[1] = GPIO(49); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/77256db5_9c2fa2eb PS36, Line 21: pins[1] = GPIO(49); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/139c4419_726add6c PS36, Line 22: pins[0] = GPIO(48); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/e1a8cb5e_09ee0b60 PS36, Line 22: pins[0] = GPIO(48); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/d8231d2d_f1cb0485 PS36, Line 26: if (id == UNDEFINED_STRAPPING_ID){ space required before the open brace '{' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136026): https://review.coreboot.org/c/coreboot/+/56642/comment/bc36fa0e_1fb88850 PS36, Line 26: if (id == UNDEFINED_STRAPPING_ID){ braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/56642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 Gerrit-Change-Number: 56642 Gerrit-PatchSet: 36 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 Dec 2021 10:49:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib: Added CBMEM tag id to parse ddr information
by Sudheer Amrabadi (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Sudheer Amrabadi, Arthur Heymans. Sudheer Amrabadi has uploaded a new patch set (#8) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/59194 ) Change subject: src/lib: Added CBMEM tag id to parse ddr information ...................................................................... src/lib: Added CBMEM tag id to parse ddr information BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 3 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59194/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f Gerrit-Change-Number: 59194 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/herobrine: Initialize SPI FW for EC and TPM
by Sudheer Amrabadi (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner, Rajesh Patil. Sudheer Amrabadi has uploaded a new patch set (#94) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/50581 ) Change subject: mb/google/herobrine: Initialize SPI FW for EC and TPM ...................................................................... mb/google/herobrine: Initialize SPI FW for EC and TPM Initialize SPI firmware for EC and H1/TPM instances for Piglin and Hoglin. Load QUP FW in respective Serial Engines. BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/herobrine/board.h M src/mainboard/google/herobrine/bootblock.c M src/mainboard/google/herobrine/chromeos.c 4 files changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/50581/94 -- To view, visit https://review.coreboot.org/c/coreboot/+/50581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Gerrit-Change-Number: 50581 Gerrit-PatchSet: 94 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: google/herobrine: configure gpio to detect board ID.
by Sudheer Amrabadi (Code Review) 22 Dec '21

22 Dec '21

Attention is currently required from: Shelley Chen, Ravi kumar, Ravi Kumar Bokka. Sudheer Amrabadi has uploaded a new patch set (#36) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/56642 ) Change subject: google/herobrine: configure gpio to detect board ID. ...................................................................... google/herobrine: configure gpio to detect board ID. BUG=b:182963902, b:193807794 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 --- M src/mainboard/google/herobrine/board.h M src/mainboard/google/herobrine/boardid.c 2 files changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/56642/36 -- To view, visit https://review.coreboot.org/c/coreboot/+/56642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 Gerrit-Change-Number: 56642 Gerrit-PatchSet: 36 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Enable building with TPM support
by Sean Rhodes (Code Review) 22 Dec '21

22 Dec '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60299 ) Change subject: payloads/tianocore: Enable building with TPM support ...................................................................... payloads/tianocore: Enable building with TPM support Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: If14441939eac86ea0f2e76ee9e7fbfc43b9c41f9 --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/60299/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 072d8d1..47967b3 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -148,6 +148,7 @@ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \ + CONFIG_TIANOCORE_TPM_SUPPORT=$(CONFIG_TIANOCORE_TPM_SUPPORT) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index b7069aa..a300232 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -112,6 +112,10 @@ useful for bootloaders that are not fully 64-bit aware such as Qubes R4.0.4 bootloader. +config TIANOCORE_TPM_SUPPORT + bool "Enable TPM Support" + default y + endif if TIANOCORE_COREBOOTPAYLOAD diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index a4ccfc7..854906e 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -46,6 +46,10 @@ 4G=-D ABOVE_4G_MEMORY=FALSE endif +ifeq ($(CONFIG_TIANOCORE_TPM_SUPPORT),y) +TPM=-DTPM_ENABLE=TRUE +endif + TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y) @@ -55,7 +59,7 @@ ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) BUILD_STR=-q -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) -DPS2_KEYBOARD_ENABLE else -BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G) +BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G) $(TPM) endif all: clean build -- To view, visit https://review.coreboot.org/c/coreboot/+/60299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If14441939eac86ea0f2e76ee9e7fbfc43b9c41f9 Gerrit-Change-Number: 60299 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021