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Change in coreboot[master]: soc/mediatek/mt8186: Add DRAM full calibration support
by build bot (Jenkins) (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60318 ) Change subject: soc/mediatek/mt8186: Add DRAM full calibration support ...................................................................... Patch Set 1: (19 comments) File src/soc/mediatek/mt8186/include/soc/dramc_soc.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/ce8cddc3_1ffcb171 PS1, Line 7: CHANNEL_A = 0, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/9fdede0e_b7b02584 PS1, Line 8: CHANNEL_B, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/976c345d_59f26722 PS1, Line 9: CHANNEL_MAX, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/62203819_73264b1b PS1, Line 13: RANK_0 = 0, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/1125c45c_cbf559a7 PS1, Line 14: RANK_1, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/b52d1ba3_82d7fa51 PS1, Line 15: RANK_MAX, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/3c6afd05_408f281f PS1, Line 20: DRAM_DFS_SHUFFLE_1 = 0, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/5cf34ced_acc17372 PS1, Line 21: DRAM_DFS_SHUFFLE_2, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/1a8aa9e6_8856f59f PS1, Line 22: DRAM_DFS_SHUFFLE_3, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/36499f5f_bbfeab3e PS1, Line 23: DRAM_DFS_SHUFFLE_4, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/4fa6d15d_42f5e8be PS1, Line 24: DRAM_DFS_SHUFFLE_5, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/320d569d_356a14c8 PS1, Line 25: DRAM_DFS_SHUFFLE_6, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/f4c9cab5_a4de0d3f PS1, Line 26: DRAM_DFS_SHUFFLE_7, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/67d6b5f1_f7518410 PS1, Line 27: DRAM_DFS_SHUFFLE_8, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/65ea16ab_29c9268f PS1, Line 28: DRAM_DFS_SHUFFLE_9, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/2ed38f88_a76fd696 PS1, Line 29: DRAM_DFS_SHUFFLE_10, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/4c0a7d83_3ff81528 PS1, Line 30: DRAM_DFS_SHUFFLE_MAX, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/7d0ff110_20ed909e PS1, Line 41: CBT_NORMAL_MODE = 0, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136072): https://review.coreboot.org/c/coreboot/+/60318/comment/e76e7257_f208bf7c PS1, Line 42: CBT_BYTE_MODE1, please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/60318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7 Gerrit-Change-Number: 60318 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 04:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus: Fix some GPIO programming
by Ariel Fang (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tim Wawrzynczak, Casper Chang. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60104 to look at the new patch set (#17). Change subject: mb/google/brya/var/primus: Fix some GPIO programming ...................................................................... mb/google/brya/var/primus: Fix some GPIO programming During the initial review, a few unused GPIOs that were inherited from the baseboard were missed, so this CL programs them as PAD_NC. GPP_B5 => I2C GPP_B6 => I2C  GPP_B15 => non-use (for FPR)  GPP_D3 => non-use (Test point)  GPP_E21 => non-use (for LCLW Detect) BUG=b:211721639 TEST= USE="project_primus" emerge-brya coreboot and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com> Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98 --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 21 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60104/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/60104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98 Gerrit-Change-Number: 60104 Gerrit-PatchSet: 17 Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/primus: Fix some GPIO programming
by Ariel Fang (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tim Wawrzynczak, Casper Chang. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60104 to look at the new patch set (#16). Change subject: mb/google/brya/var/primus: Fix some GPIO programming ...................................................................... mb/google/brya/var/primus: Fix some GPIO programming -During the initial review, a few unused GPIOs that were inherited from the baseboard were missed, so this CL programs them as PAD_NC. GPP_B5 => I2C GPP_B6 => I2C  GPP_B15 => non-use (for FPR)  GPP_D3 => non-use (Test point)  GPP_E21 => non-use (for LCLW Detect) BUG=b:211721639 TEST= USE="project_primus" emerge-brya coreboot and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com> Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98 --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 21 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60104/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/60104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98 Gerrit-Change-Number: 60104 Gerrit-PatchSet: 16 Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add devapc basic drivers
by build bot (Jenkins) (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60317 ) Change subject: soc/mediatek/mt8186: Add devapc basic drivers ...................................................................... Patch Set 1: (11 comments) File src/soc/mediatek/mt8186/devapc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/5665cbb0_fdd9c720 PS1, Line 23: DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SLEEP_CONTROLER", 'CONTROLER' may be misspelled - perhaps 'CONTROLLER'? File src/soc/mediatek/mt8186/include/soc/devapc.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/c312d7e8_9e38d321 PS1, Line 66: #define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/1c785f23_08068d7b PS1, Line 71: #define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/30be648d_f7ffa018 PS1, Line 79: #define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/f84a110c_dc8e20ea PS1, Line 93: #define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/ee86643c_90beb1e4 PS1, Line 94: #define FORBIDDEN4 FORBIDDEN3, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/9a6e83ad_b5649808 PS1, Line 95: #define FORBIDDEN5 FORBIDDEN4, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/b65ef48e_bab06c9d PS1, Line 96: #define FORBIDDEN6 FORBIDDEN5, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/167d48f4_68dc0df9 PS1, Line 97: #define FORBIDDEN7 FORBIDDEN6, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/253d74d0_0e2e0633 PS1, Line 99: #define NO_PROTECTION4 NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136071): https://review.coreboot.org/c/coreboot/+/60317/comment/b56e7318_0a80b2c2 PS1, Line 123: DEFINE_BIT(SCP_SSPM_SEC,21) space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/60317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Gerrit-Change-Number: 60317 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 04:33:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add DRAM full calibration support
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Hung-Te Lin, Ryan Chuang. Hello Ryan Chuang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60318 to review the following change. Change subject: soc/mediatek/mt8186: Add DRAM full calibration support ...................................................................... soc/mediatek/mt8186: Add DRAM full calibration support Initialize and calibrate DRAM in romstage. We remove emi.h because emi.h is defined in common/include/soc. TEST=DRAM full calibration pass. BUG=b:202871018 Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7 --- M src/mainboard/google/corsola/Makefile.inc M src/mainboard/google/corsola/romstage.c A src/mainboard/google/corsola/sdram_configs.c M src/soc/mediatek/mt8186/Kconfig M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/emi.c A src/soc/mediatek/mt8186/include/soc/dramc_param.h A src/soc/mediatek/mt8186/include/soc/dramc_soc.h D src/soc/mediatek/mt8186/include/soc/emi.h 9 files changed, 239 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/60318/1 diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index 1a9a1c28..e1e363c 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -11,6 +11,7 @@ romstage-y += chromeos.c romstage-y += regulator.c romstage-y += romstage.c +romstage-y += sdram_configs.c ramstage-y += memlayout.ld ramstage-y += boardid.c diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c index aff496b..8d03b5b 100644 --- a/src/mainboard/google/corsola/romstage.c +++ b/src/mainboard/google/corsola/romstage.c @@ -3,6 +3,7 @@ #include <arch/stages.h> #include <console/console.h> #include <delay.h> +#include <soc/emi.h> #include <soc/mt6366.h> #include <soc/pll_common.h> #include <soc/regulator.h> @@ -26,4 +27,5 @@ mt6366_init(); raise_little_cpu_freq(); rtc_boot(); + mtk_dram_init(); } diff --git a/src/mainboard/google/corsola/sdram_configs.c b/src/mainboard/google/corsola/sdram_configs.c new file mode 100644 index 0000000..f565f53 --- /dev/null +++ b/src/mainboard/google/corsola/sdram_configs.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +const struct sdram_info *get_sdram_config(void) +{ + /* + * The MT8186 platform supports "dram adaptive" feature to + * automatically detect dram information, including channel, rank, die size..., + * and can automatically configure EMI settings. + * So we will be passing a placeholder param blob. + */ + static struct sdram_info params; + return &params; +} diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index 5393baa..11a18f2 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -6,6 +6,7 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select ARM64_USE_ARM_TRUSTED_FIRMWARE + select CACHE_MRC_SETTINGS select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 5d3f668..c940d37 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -26,10 +26,14 @@ romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c +romstage-y += ../common/memory.c +romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -78,6 +82,14 @@ $(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \ ) +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8186_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c index 169b353..48a7b3e 100644 --- a/src/soc/mediatek/mt8186/emi.c +++ b/src/soc/mediatek/mt8186/emi.c @@ -11,3 +11,8 @@ { return (size_t)4 * GiB; } + +void mt_set_emi(struct dramc_param *dparam) +{ + /* Do nothing */ +} diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_param.h b/src/soc/mediatek/mt8186/include/soc/dramc_param.h new file mode 100644 index 0000000..00dc0a5 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dramc_param.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ + +/* + * NOTE: This file is shared between coreboot and dram blob. Any change in this + * file should be synced to the other repository. + */ + +#include <stdint.h> +#include <sys/types.h> +#include <soc/dramc_soc.h> + +#define DRAMC_PARAM_HEADER_VERSION 1 + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, + DRAMC_ERR_INIT_DRAM, + DRAMC_ERR_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_FAST_CALIBRATION, +}; + +enum DRAMC_PARAM_FLAGS { + DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, +}; + +enum SDRAM_DVFS_FLAG { + DRAMC_DISABLE_DVFS, + DRAMC_ENABLE_DVFS, +}; + +enum SDRAM_DDR_TYPE { + DDR_TYPE_DISCRETE, + DDR_TYPE_EMCP, +}; + +enum SDRAM_DDR_GEOMETRY_TYPE { + DDR_TYPE_2CH_2RK_4GB_2_2, + DDR_TYPE_2CH_2RK_6GB_3_3, + DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, + DDR_TYPE_2CH_1RK_4GB_4_0, + DDR_TYPE_2CH_2RK_6GB_2_4, + DDR_TYPE_2CH_2RK_8GB_4_4, +}; + +enum SDRAM_VOLTAGE_TYPE { + SDRAM_VOLTAGE_NVCORE_NVDRAM, + SDRAM_VOLTAGE_HVCORE_HVDRAM, + SDRAM_VOLTAGE_LVCORE_LVDRAM, +}; + +struct dramc_param_header { + u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ + u16 size; /* size of whole dramc_param, update in the coreboot */ + u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ + u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ +}; + +struct sdram_info { + u32 ddr_type; /* SDRAM_DDR_TYPE */ + u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ +}; + +struct sdram_params { + u32 rank_num; + u16 num_dlycell_perT; + u16 delay_cell_timex100; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + + /* CBT */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + s8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* Gating */ + u8 gating_MCK[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* TX perbit */ + u8 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit */ + u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* TX OE */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; +}; + +struct emi_mdl { + u32 cona_val; + u32 conh_val; + u32 conf_val; + u32 chn_cona_val; +}; + +struct ddr_base_info { + u32 config_dvfs; /* SDRAM_DVFS_FLAG */ + struct sdram_info sdram; + u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ + u32 support_ranks; + u64 rank_size[RANK_MAX]; + struct emi_mdl emi_config; + DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +const struct sdram_info *get_sdram_config(void); +struct dramc_param *get_dramc_param_from_blob(void *blob); +void dump_param_header(const void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob); +#endif /* __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h new file mode 100644 index 0000000..465323b --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ +#define __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ + +typedef enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX, +} DRAM_CHANNEL_T; + +typedef enum { + RANK_0 = 0, + RANK_1, + RANK_MAX, +} DRAM_RANK_T; + +/* DRAM SHUFFLE RG type */ +typedef enum { + DRAM_DFS_SHUFFLE_1 = 0, + DRAM_DFS_SHUFFLE_2, + DRAM_DFS_SHUFFLE_3, + DRAM_DFS_SHUFFLE_4, + DRAM_DFS_SHUFFLE_5, + DRAM_DFS_SHUFFLE_6, + DRAM_DFS_SHUFFLE_7, + DRAM_DFS_SHUFFLE_8, + DRAM_DFS_SHUFFLE_9, + DRAM_DFS_SHUFFLE_10, + DRAM_DFS_SHUFFLE_MAX, +} DRAM_DFS_SHUFFLE_TYPE_T; + +/* + * Internal CBT mode enum + * 1. Calibration flow uses vGet_Dram_CBT_Mode to + * differentiate between mixed vs non-mixed LP4 + * 2. Declared as dram_cbt_mode[RANK_MAX] internally to + * store each rank's CBT mode type + */ +typedef enum { + CBT_NORMAL_MODE = 0, + CBT_BYTE_MODE1, +} DRAM_CBT_MODE_T; + +#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX + +#define DQS_NUMBER_LP4 2 +#define DQS_BIT_NUMBER 8 +#define DQ_DATA_WIDTH_LP4 16 + +#endif /* __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/emi.h b/src/soc/mediatek/mt8186/include/soc/emi.h deleted file mode 100644 index decfa07..0000000 --- a/src/soc/mediatek/mt8186/include/soc/emi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is created based on MT8186 Functional Specification - * Chapter number: 4.8 - */ - -#ifndef SOC_MEDIATEK_MT8186_EMI_H -#define SOC_MEDIATEK_MT8186_EMI_H - -#include <stddef.h> - -size_t sdram_size(void); - -#endif /* SOC_MEDIATEK_MT8186_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7 Gerrit-Change-Number: 60318 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add devapc basic drivers
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60317 ) Change subject: soc/mediatek/mt8186: Add devapc basic drivers ...................................................................... soc/mediatek/mt8186: Add devapc basic drivers Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set default permission. BUG=b:202871018 TEST=build pass Signed-off-by: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/devapc.c A src/soc/mediatek/mt8186/include/soc/devapc.h M src/soc/mediatek/mt8186/soc.c 4 files changed, 1,450 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/60317/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 2a22e6e..5d3f668 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -40,6 +40,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += ../common/auxadc.c +ramstage-y += devapc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8186/devapc.c b/src/soc/mediatek/mt8186/devapc.c new file mode 100644 index 0000000..dcb468c --- /dev/null +++ b/src/soc/mediatek/mt8186/devapc.c @@ -0,0 +1,1322 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/devapc.h> +static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = { + /* 0 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPCKGEN", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_INFRASYS_CONFIG_REGS", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("IO_CFG_REG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_ PERICFG", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_EFUSAO_DEBUG", + SEC_RW_NS_R, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_GPIO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SLEEP_CONTROLER", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPRGU", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APXGPT", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_RESERVE", + NO_PROTECTION, FORBIDDEN7), + + /* 10 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SEJ", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_AP_CIRQ_EINT", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APMIXEDSYS", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIC_WRAP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_INFRA_PERI", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_MM", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_KEYPAD", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOP_MISC", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_ DVFS_CTRL_PROC", + NO_PROTECTION, SEC_RW_NS_R, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_IFNRA_TOP_MBIST_CTRL", + NO_PROTECTION, FORBIDDEN7), + + /* 20 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DPMAIF_AO_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_AES_TOP_0", + FORBIDDEN, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SYS_TIMER", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_MDEM_TEMP_SHARE", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_MD", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SECURITY_AO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPMI_MST_WRAP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + + /* 30 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_AP_DMA", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_SYS_CIRQ", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DEVICAPC", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DBG_TRACKER", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + + /* 40 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF0_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF0_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF1_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF1_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_INFRA_PDN_REGISTER", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_TRNG", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DX_CC", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF4_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN, + NO_PROTECTION, FORBIDDEN4), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CQ_DMA", + NO_PROTECTION, FORBIDDEN7), + + /* 50 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF4_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, + NO_PROTECTION, FORBIDDEN4), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_SRAMROM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_EMI", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DEVICMPU_LOW", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_EMI_MPU_REG", + SEC_RW_NS_R, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + + /* 60 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP1", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP2", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP4", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP6", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + + /* 70 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_GCE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP0", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP1", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP2", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP4", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP6", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF2_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF2_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + + /* 80 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF3_AP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF3_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_1", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_2", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_2", + SEC_RW_NS_R, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_4", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_6", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + + /* 90 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_7", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_8", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SCP", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_MCUCFG(*)", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DBUGSYS", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUXADC", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART0", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C7", + NO_PROTECTION, FORBIDDEN7), + + /* 100 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C8", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_PWM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_PTP", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_BTIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C6", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_DISP_PWM", + NO_PROTECTION, FORBIDDEN7), + + /* 110 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C4", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI4", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI5", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C5", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_IMP_IIC_WRAP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART2", + NO_PROTECTION, FORBIDDEN7), + + /* 120 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C9", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN5, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB_2.0_SUB", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UFS", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISUS_USB3.0_SIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISUS_USB3.0_SIF2", + NO_PROTECTION, FORBIDDEN7), + + /* 130 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB_2.0_SIF(**)", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIO", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("EAST_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ CSI_TOP_AO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + + /* 140 */ + DAPC_INFRA_AO_SYS0_ATTR("WEST_MIPI_TX_CONFIG", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("WEST_MSDC1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("WEST_USB20_PHY", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("WEST_EFUSE", + NO_PROTECTION, SEC_RW_NS_R, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_UFS_MPHY", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_MSDC0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_RESERV0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_RESERV1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_CONN", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + FORBIDDEN3, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MD1", + NO_PROTECTION, FORBIDDEN7), + + /* 150 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIODSP", + NO_PROTECTION, FORBIDDEN7), +}; + +/* module, AP permission, N/A, SSPM permission, N/A */ +static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = { + + /* 0 */ + DAPC_MM_AO_SYS0_ATTR("IP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DFD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D Secure Reg", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D TestBench", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D_CONFIG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MMSYS_CONFIG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_MUTEX0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 10 */ + DAPC_MM_AO_SYS0_ATTR("SMI_COMMON", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("SMI_LARB0", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("SMI_LARB1", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("DISP_OVL0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_OVL0_2L", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_RDMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_RSZ0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_COLOR0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_CCORR0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 20 */ + DAPC_MM_AO_SYS0_ATTR("DISP_AAL0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_GAMMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_POSTMASK0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_DITHER0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_DSC_WRAP0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DSI0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_WDMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 30 */ + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_SMI_2X1_SUB_COMMON_U0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_SMI_2X1_SUB_COMMON_U1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("IMG1_SMI_2X1_SUB_COMMON", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 40 */ + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (mfb_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (wpe_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (mss_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 50 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("imgsys1_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 60 */ + DAPC_MM_AO_SYS0_ATTR("dip_a2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a5", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a6", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a7", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a9)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a10", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a11", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 70 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb9", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("2x1_sub_common", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mfb_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("wpe_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mss_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 80 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("imgsys2_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 90 */ + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b0)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b1)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b2)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b3)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b4)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b5)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b6)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b7)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 100 */ + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b9)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b10)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b11)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb11", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("reserved (smi_larb12)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("rserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 110 */ + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 120 */ + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0_larb", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("vdec_core0_gcon", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_mini_mdp_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("venc_global_con", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb7", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("venc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("jpgenc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 130 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("venc_mbist_ctrl", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb13", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("smi_larb14", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_a", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_c", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 140 */ + DAPC_MM_AO_SYS0_ATTR("seninf_d", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_e", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_f", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_g", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_h", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_smi_3x1_sub_common_u0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_smi_4x1_sub_common_u0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb_16", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("smi_larb_17", + NO_PROTECTION4), + + /* 150 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 160 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 170 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 180 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 190 */ + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 200 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_set", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_clr", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_set_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_clr_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 210 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys_a_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 220 */ + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 230 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_set", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_clr", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 240 */ + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_set_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_clr_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys_b_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 250 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 260 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 270 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 280 */ + DAPC_MM_AO_SYS0_ATTR("camsv_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_5", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_6", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_7", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_4_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 290 */ + DAPC_MM_AO_SYS0_ATTR("camsv_5_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_6_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_7_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("asg", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 300 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 310 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdpsys_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 320 */ + DAPC_MM_AO_SYS0_ATTR("mdp_mutex0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb0", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("mdp_rdma0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_aal0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_hdr0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_rsz0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_rsz1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_wrot0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 330 */ + DAPC_MM_AO_SYS0_ATTR("mdp_wrot1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_tdshp0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ipesys_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("fdvt", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved (fe)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("rsc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 340 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ipe_smi_2x1_sub_common", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 350 */ + DAPC_MM_AO_SYS0_ATTR("smi_larb20", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("depth", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 360 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb19", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION) +}; + +static const enum domain_id domain_map[] = { + DOMAIN_0, DOMAIN_1, DOMAIN_2, DOMAIN_3, + DOMAIN_4, DOMAIN_5, DOMAIN_6, DOMAIN_7, + DOMAIN_8, DOMAIN_9, DOMAIN_10, DOMAIN_11, + DOMAIN_12, DOMAIN_13, DOMAIN_14, DOMAIN_15, +}; + +static inline void *getreg_domain(uintptr_t base, unsigned int offset, + enum domain_id domain_id, unsigned int index) +{ + return (void *)(base + offset + domain_id * 0x100 + index * 0x4); +} + +static inline void *getreg(uintptr_t base, unsigned int offset) +{ + return getreg_domain(base, offset, 0, 0); +} + +static void set_module_apc(uintptr_t base, uint32_t module, enum domain_id domain_id, + enum devapc_perm_type perm) +{ + uint32_t apc_register_index; + uint32_t apc_set_index; + + apc_register_index = module / MOD_NO_IN_1_DEVAPC; + apc_set_index = module % MOD_NO_IN_1_DEVAPC; + + clrsetbits32(getreg_domain(base, 0, domain_id, apc_register_index), + 0x3 << (apc_set_index * 2), + perm << (apc_set_index * 2)); +} + +static void set_infra_ao_apc(uintptr_t base) +{ + int i, j; + + for (i = 0; i < ARRAY_SIZE(infra_ao_sys0_devices); i++) + for (j = 0; j < ARRAY_SIZE(infra_ao_sys0_devices[i].d_permission); j++) + set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], + infra_ao_sys0_devices[i].d_permission[j]); +} + +static void set_mm_ao_apc(uintptr_t base) +{ + int i, j; + + for (i = 0; i < ARRAY_SIZE(mm_ao_sys0_devices); i++) + for (j = 0; j < ARRAY_SIZE(mm_ao_sys0_devices[i].d_permission); j++) + set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], + mm_ao_sys0_devices[i].d_permission[j]); + /* + * Extra apc setting. + * Block debugsys to avoid privilege escalation. + */ + if (!CONFIG(CONSOLE_SERIAL)) + set_module_apc(base + SYS0_D0_APC_0, DEVAPC_DEBUGSYS_INDEX, + DOMAIN_0, SEC_RW_NS_R); + +} + +static void dump_infra_ao_apc(uintptr_t base) +{ + int reg_max; + int d, i; + + reg_max = DIV_ROUND_UP(ARRAY_SIZE(infra_ao_sys0_devices), MOD_NO_IN_1_DEVAPC); + for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++) + for (i = 0; i < reg_max; i++) + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: %#x\n", d, i, + read32(getreg_domain(base, SYS0_D0_APC_0, d, i))); + + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO)MAS_SEC_0: %#x\n", + read32(getreg(base, MAS_SEC_0))); +} + +static void dump_mm_ao_apc(uintptr_t base) +{ + int reg_max; + int d, i; + + reg_max = DIV_ROUND_UP(ARRAY_SIZE(mm_ao_sys0_devices), MOD_NO_IN_1_DEVAPC); + for (d = 0; d < DOM_NUM_MM_AO_SYS0; d++) + for (i = 0; i < reg_max; i++) + printk(BIOS_DEBUG, "[DEVAPC] (MM_AO_SYS0)D%d_APC_%d: %#x\n", d, i, + read32(getreg_domain(base, SYS0_D0_APC_0, d, i))); + + printk(BIOS_DEBUG, "[DEVAPC] (MM_AO)MAS_SEC_0: %#x\n", + read32(getreg(base, MAS_SEC_0))); +} + +static void infra_init(uintptr_t base) +{ + + /* Side band */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, SECURE_TRANS); + + /* Default APC Setting */ + set_infra_ao_apc(base); +} + +static void mm_init(uintptr_t base) +{ + /* Default APC Setting */ + set_mm_ao_apc(base); +} + +struct devapc_init_ops { + uintptr_t base; + void (*init)(uintptr_t base); + void (*dump)(uintptr_t base); +} devapc_init[] = { + { DEVAPC_AO_INFRA_PERI_BASE, infra_init, dump_infra_ao_apc }, + { DEVAPC_AO_MM_BASE, mm_init, dump_mm_ao_apc }, +}; + +void dapc_init(void) +{ + int i; + uintptr_t devapc_ao_base; + + for (i = 0; i < ARRAY_SIZE(devapc_init); i++) { + devapc_ao_base = devapc_init[i].base; + + /* Init dapc */ + write32(getreg(devapc_ao_base, AO_APC_CON), 0x0); + + /* Initialization */ + if (devapc_init[i].init) + devapc_init[i].init(devapc_ao_base); + + /* Dump Setting */ + if (devapc_init[i].dump) + devapc_init[i].dump(devapc_ao_base); + } +} diff --git a/src/soc/mediatek/mt8186/include/soc/devapc.h b/src/soc/mediatek/mt8186/include/soc/devapc.h new file mode 100644 index 0000000..96801a7 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/devapc.h @@ -0,0 +1,125 @@ +#ifndef SOC_MEDIATEK_MT8186_DEVAPC_H +#define SOC_MEDIATEK_MT8186_DEVAPC_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void dapc_init(void); + +enum devapc_ao_offset { + SYS0_D0_APC_0 = 0x0, + DOM_REMAP_0_0 = 0xD00, + DOM_REMAP_1_0 = 0xD04, + MAS_DOM_0 = 0x0A00, + MAS_SEC_0 = 0x0B00, + AO_APC_CON = 0x0F00, +}; + +/****************************************************************************** + * STRUCTURE DEFINITION + ******************************************************************************/ +/* Common */ +enum trans_type { + NON_SECURE_TRANS = 0, + SECURE_TRANS, +}; + +enum devapc_perm_type { + NO_PROTECTION = 0, + SEC_RW_ONLY, + SEC_RW_NS_R, + FORBIDDEN, + PERM_NUM, +}; + +enum domain_id { + DOMAIN_0 = 0, + DOMAIN_1, + DOMAIN_2, + DOMAIN_3, + DOMAIN_4, + DOMAIN_5, + DOMAIN_6, + DOMAIN_7, + DOMAIN_8, + DOMAIN_9, + DOMAIN_10, + DOMAIN_11, + DOMAIN_12, + DOMAIN_13, + DOMAIN_14, + DOMAIN_15, +}; + +struct apc_infra_peri_dom_16 { + unsigned char d_permission[16]; +}; + +struct apc_infra_peri_dom_8 { + unsigned char d_permission[8]; +}; + +struct apc_infra_peri_dom_4 { + unsigned char d_permission[4]; +}; + +#define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, + +#define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) + +#define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, \ + PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, \ + PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) + +#define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN +#define FORBIDDEN4 FORBIDDEN3, FORBIDDEN +#define FORBIDDEN5 FORBIDDEN4, FORBIDDEN +#define FORBIDDEN6 FORBIDDEN5, FORBIDDEN +#define FORBIDDEN7 FORBIDDEN6, FORBIDDEN + +#define NO_PROTECTION4 NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION + +enum devapc_sys_dom_num { + DOM_NUM_INFRA_AO_SYS0 = 8, + DOM_NUM_MM_AO_SYS0 = 4, +}; + +enum devapc_cfg_index { + DEVAPC_DEBUGSYS_INDEX = 17, +}; + +/* PERM_ATTR MACRO */ +#define DAPC_INFRA_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_8(__VA_ARGS__) } } +#define DAPC_MM_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_4(__VA_ARGS__) } } + +/****************************************************************************** + * Variable DEFINITION + ******************************************************************************/ +#define MOD_NO_IN_1_DEVAPC 16 + +/****************************************************************************** + * Bit Field DEFINITION + ******************************************************************************/ +/* INFRA */ +DEFINE_BIT(SCP_SSPM_SEC,21) + +#endif diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c index e20b447..3ad83f7 100644 --- a/src/soc/mediatek/mt8186/soc.c +++ b/src/soc/mediatek/mt8186/soc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <soc/devapc.h> #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> @@ -15,6 +16,7 @@ { mtk_mmu_disable_l2c_sram(); sspm_init(); + dapc_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/60317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Gerrit-Change-Number: 60317 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: adjust usage of SRAM L2C
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60316 ) Change subject: soc/mediatek/mt8186: adjust usage of SRAM L2C ...................................................................... soc/mediatek/mt8186: adjust usage of SRAM L2C The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM has configured only half of L2/L3 cache as SRAM. Therefore, decrease the size of each SRAM region to fit into the first half of the cache. BUG=b:207725851 TEST=Bootblock log looked good in `cbmem -c` Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 --- M src/soc/mediatek/mt8186/include/soc/memlayout.ld 1 file changed, 10 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60316/1 diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index a1700e6..a409feb 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -34,6 +34,11 @@ /* MT8186 has 64KB SRAM. */ SRAM_END(0x00110000) + /* + * The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM + * has configured only half of L2/L3 cache as SRAM so we can't use them + * unless if we disable L2C and reconfigure. + */ SRAM_L2C_START(0x00200000) /* 4K reserved for BOOTROM until BOOTBLOCK is started */ BOOTBLOCK(0x00201000, 60K) @@ -41,11 +46,11 @@ * The needed size can be obtained by: * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz */ - DRAM_INIT_CODE(0x00210000, 240K) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K) - PRERAM_CBFS_CACHE(0x00290000, 48K) - PRERAM_CBMEM_CONSOLE(0x0029C000, 400K) - SRAM_L2C_END(0x00300000) + DRAM_INIT_CODE(0x00210000, 196K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00241000, 140K) + PRERAM_CBFS_CACHE(0x00264000, 48K) + PRERAM_CBMEM_CONSOLE(0x00270000, 64K) + SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) -- To view, visit https://review.coreboot.org/c/coreboot/+/60316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 Gerrit-Change-Number: 60316 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Hung-Te Lin, Tianping Fang, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60312 ) Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60312/comment/e8f87dea_180150be PS3, Line 9: a > an Done https://review.coreboot.org/c/coreboot/+/60312/comment/afad44b9_cacbad8e PS3, Line 10: MT8195 > can you explain why this is not a problem for 8183 and 8192? silicon design issue or? it's a design issue for mt8195, and I have added this comment to commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 04:28:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tianping Fang, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60312 ) Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 04:27:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Rex-BC Chen (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Tianping Fang, Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Tianping Fang, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60312 to look at the new patch set (#4). Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... soc/medaitek/mt8195: adjust USB phy shift value There is a design issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefore, we add this patch to set USB phy registers from value of efuse. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Signed-off-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Tested-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 --- M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c M src/soc/mediatek/mt8195/include/soc/usb.h M src/soc/mediatek/mt8195/usb.c 4 files changed, 61 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/60312/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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