coreboot-gerrit December 2021

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Change in coreboot[master]: util/liveiso: Merge build scripts
by Michael Niewöhner (Code Review) 26 Dec '21

26 Dec '21

Attention is currently required from: Felix Singer. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60372 ) Change subject: util/liveiso: Merge build scripts ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File util/liveiso/build.sh: https://review.coreboot.org/c/coreboot/+/60372/comment/aa72387c_89186793 PS1, Line 6: echo "No config given. Exiting." maybe also print usage like this? "Usage: build.sh <graphical.nix|console.nix|...>" https://review.coreboot.org/c/coreboot/+/60372/comment/faddfbc1_12c28ca5 PS1, Line 12: nixos-config=$config could be `nixos-config=${config}.nix` - not requirement, just some random idea :) -- To view, visit https://review.coreboot.org/c/coreboot/+/60372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49360a5c57954a205c697a4ae07361779db2aa83 Gerrit-Change-Number: 60372 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Sun, 26 Dec 2021 10:23:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Make more brya variants to choose eNEM for CAR
by Felix Singer (Code Review) 26 Dec '21

26 Dec '21

Attention is currently required from: David Wu, Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60377 ) Change subject: mb/google/brya: Make more brya variants to choose eNEM for CAR ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60377/comment/1c14714c_f244ca3d PS2, Line 7: Make more brya variants to choose eNEM for CAR > This is good suggestion Felix, but I will keep this patch open for one more week to see if any more […] Oh sure 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/60377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5734606e58410545a5f5421837080680664707f Gerrit-Change-Number: 60377 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quantatw.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 26 Dec 2021 10:09:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Felix Held (Code Review) 26 Dec '21

26 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60312 ) Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... soc/medaitek/mt8195: adjust USB phy shift value There is a design issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefore, we add this patch to set USB phy registers from value of efuse. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Signed-off-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Tested-by: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c M src/soc/mediatek/mt8195/include/soc/usb.h M src/soc/mediatek/mt8195/usb.c 4 files changed, 61 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index 6fa050d..d390b70 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -130,9 +130,13 @@ check_member(sif_u2_phy_com, u2phydtm0, 0x68); struct sif_u3phyd { - u32 reserved0[23]; + u32 reserved0[4]; + u32 phyd_cal0; + u32 phyd_cal1; + u32 reserved1[15]; + u32 phyd_reserved; u32 phyd_cdr1; - u32 reserved1[40]; + u32 reserved2[41]; }; struct sif_u3phya { @@ -155,6 +159,7 @@ * SOCs will not need it. */ void mtk_usb_prepare(void); +void mtk_usb_adjust_phy_shift(void); void setup_usb_host(void); diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index 52daaac..b9fe835 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -140,7 +140,15 @@ clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); } -__weak void mtk_usb_prepare(void) { /* do nothing */ } +__weak void mtk_usb_prepare(void) +{ + /* do nothing */ +} + +__weak void mtk_usb_adjust_phy_shift(void) +{ + /* do nothing */ +} void setup_usb_host(void) { @@ -153,5 +161,6 @@ return; } u3phy_power_on(); + mtk_usb_adjust_phy_shift(); u3p_msg("phy power-on done.\n"); } diff --git a/src/soc/mediatek/mt8195/include/soc/usb.h b/src/soc/mediatek/mt8195/include/soc/usb.h index e39ec38..c3b3c58 100644 --- a/src/soc/mediatek/mt8195/include/soc/usb.h +++ b/src/soc/mediatek/mt8195/include/soc/usb.h @@ -19,6 +19,21 @@ check_member(ssusb_sif_port, u3phya_da, 0x900); check_member(ssusb_sif_port, reserved2, 0xa00); -#define USB_PORT_NUMBER 1 +DEFINE_BIT(AUTO_LOAD_DIS, 12) +DEFINE_BITFIELD(TX_IMP_CAL, 28, 24) +DEFINE_BIT(TX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(RX_IMP_CAL, 28, 24) +DEFINE_BIT(RX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(INTR_CAL, 15, 10) + +#define TX_IMP_MASK 0x1F +#define TX_IMP_SHIFT 0 +#define RX_IMP_MASK 0x3E0 +#define RX_IMP_SHIFT 5 +#define INTR_CAL_MASK 0xFC00 +#define INTR_CAL_SHIFT 10 + +#define USB_PHY_SETTING_REG 0x11C10184 +#define USB_PORT_NUMBER 1 #endif diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c index 7b6347e..b3f00a9 100644 --- a/src/soc/mediatek/mt8195/usb.c +++ b/src/soc/mediatek/mt8195/usb.c @@ -10,3 +10,31 @@ setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15)); setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31)); } + +void mtk_usb_adjust_phy_shift(void) +{ + u32 phy_set_val, write_val; + struct ssusb_sif_port *phy = (void *)(SSUSB_SIF_BASE); + + SET32_BITFIELDS(&phy->u3phyd.phyd_reserved, + AUTO_LOAD_DIS, 1); + + phy_set_val = read32((void *)USB_PHY_SETTING_REG); + + /* TX imp */ + write_val = (phy_set_val & TX_IMP_MASK) >> TX_IMP_SHIFT; + SET32_BITFIELDS(&phy->u3phyd.phyd_cal0, + TX_IMP_CAL, write_val, + TX_IMP_CAL_EN, 1); + + /* RX imp */ + write_val = (phy_set_val & RX_IMP_MASK) >> RX_IMP_SHIFT; + SET32_BITFIELDS(&phy->u3phyd.phyd_cal1, + RX_IMP_CAL, write_val, + RX_IMP_CAL_EN, 1); + + /* Intr_cal */ + write_val = (phy_set_val & INTR_CAL_MASK) >> INTR_CAL_SHIFT; + SET32_BITFIELDS(&phy->u3phya.phya_reg0, + INTR_CAL, write_val); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/taeko4es: Set vGPIO reset type
by Felix Held (Code Review) 26 Dec '21

26 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60186 ) Change subject: mb/google/brya/var/taeko4es: Set vGPIO reset type ...................................................................... mb/google/brya/var/taeko4es: Set vGPIO reset type Copied from commit df72b18d (mb/google/brya/var/taeko: Set vGPIO reset type).Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack. BUG=b:207070967 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60186 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taeko4es/gpio.c 1 file changed, 20 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c index 17018cd..aa778fc 100644 --- a/src/mainboard/google/brya/variants/taeko4es/gpio.c +++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c @@ -175,26 +175,26 @@ */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* CPU PCIe VGPIO for PEG60 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; const struct pad_config *variant_gpio_override_table(size_t *num) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782 Gerrit-Change-Number: 60186 Gerrit-PatchSet: 4 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{skl,cnl}: Guard USB macro parameters
by Felix Held (Code Review) 26 Dec '21

26 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60324 ) Change subject: soc/intel/{skl,cnl}: Guard USB macro parameters ...................................................................... soc/intel/{skl,cnl}: Guard USB macro parameters Add parentheses around the parameter of the `USB_PORT_WAKE_ENABLE` macro to prevent unintentional operator precedence problems. Change-Id: I61fbacc129cbfb42ade7e64ee40cd07c98d87683 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60324 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/include/soc/usb.h M src/soc/intel/skylake/include/soc/usb.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 66b3f8b..20b3149 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -191,6 +191,6 @@ * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. */ -#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1)) +#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) #endif diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index d87c859..7912603 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -185,6 +185,6 @@ * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. */ -#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1)) +#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/60324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61fbacc129cbfb42ade7e64ee40cd07c98d87683 Gerrit-Change-Number: 60324 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/acer/g43t-am3: Add documentation
by Felix Held (Code Review) 26 Dec '21

26 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56838 ) Change subject: mb/acer/g43t-am3: Add documentation ...................................................................... mb/acer/g43t-am3: Add documentation Signed-off-by: Michael Büchler <michael.buechler(a)posteo.net> Change-Id: I0e296b3efbff0260f32badc699f1062f9885fa53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56838 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A Documentation/mainboard/acer/g43t-am3.md M Documentation/mainboard/index.md 2 files changed, 181 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/mainboard/acer/g43t-am3.md b/Documentation/mainboard/acer/g43t-am3.md new file mode 100644 index 0000000..2e9b8d6 --- /dev/null +++ b/Documentation/mainboard/acer/g43t-am3.md @@ -0,0 +1,177 @@ +# Acer G43T-AM3 + +The Acer G43T-AM3 is a microATX-sized desktop board. It was used for the +Acer models Aspire M3800, Aspire M5800 and possibly more. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | Intel G43 (called x4x in coreboot code) | ++------------------+--------------------------------------------------+ +| Southbridge | Intel ICH10R (called i82801jx in coreboot code) | ++------------------+--------------------------------------------------+ +| CPU socket | LGA 775 | ++------------------+--------------------------------------------------+ +| RAM | 4 x DDR3-1066 | ++------------------+--------------------------------------------------+ +| SuperIO | ITE IT8720F | ++------------------+--------------------------------------------------+ +| Audio | Realtek ALC888S | ++------------------+--------------------------------------------------+ +| Network | Intel 82567V-2 Gigabit Ethernet | ++------------------+--------------------------------------------------+ +``` + +There is no serial port. Serial console output is possible by soldering +to a point at the corresponding Super I/O pin and patching the +mainboard-specific code accordingly. + +## Status + +### Working + +Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12 +(linux-4.19.50). + ++ Intel Core 2 processors at up to FSB 1333 ++ All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB) ++ Integrated graphics (libgfxinit) ++ HDMI and VGA ports ++ Both PCI slots ++ Both PCI-e slots ++ USB (8 internal, 4 external) ++ All six SATA ports ++ Onboard Ethernet ++ Onboard sound card with output on the rear stereo connector ++ PS/2 mouse and keyboard + + With SeaBIOS, use CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500 + + With FILO it works without further settings ++ Temperature readings from the Super I/O (including the CPU temperature + via PECI) ++ Super I/O EC automatic fan control ++ S3 suspend/resume ++ Poweroff + +### Not working + ++ DDR3 memory with 512Mx8 chips (G43 limitation) ++ 4x4GB of DDR3 memory (works, but showed a single bit error within one + pass of Memtest86+ 5.01) ++ Super I/O voltage reading conversions + +### Untested + ++ Other audio jacks or the front panel header ++ S/PDIF output ++ On-board Firewire ++ Wake-on-LAN + +## Flashing coreboot + +```eval_rst ++-------------------+---------------------+ +| Type | Value | ++===================+=====================+ +| Socketed flash | No | ++-------------------+---------------------+ +| Model | Macronix MX25L1605D | ++-------------------+---------------------+ +| Size | 2 MiB | ++-------------------+---------------------+ +| Package | 8-Pin SOP | ++-------------------+---------------------+ +| Write protection | No | ++-------------------+---------------------+ +| Dual BIOS feature | No | ++-------------------+---------------------+ +| Internal flashing | Yes | ++-------------------+---------------------+ +``` + +The flash is divided into the following regions, as obtained with +`ifdtool -f rom.layout backup.rom`: +``` +00000000:00001fff fd +00100000:001fffff bios +00006000:000fffff me +00002000:00005fff gbe +``` + +In general, flashing is possible internally and from an external header. It +might be necessary to specify the chip type; `MX25L1605D/MX25L1608D/MX25L1673E` +is the correct one, not `MX25L1605`. + +### Internal flashing + +Internal access to the flash chip is unrestricted. When installing coreboot, +only the BIOS region should be updated by passing the `--ifd` and `-i bios` +parameters to flashrom. A full backup is advisable. + +Here is an example: + +``` +$ sudo flashrom \ + -p internal \ + -c "MX25L1605D/MX25L1608D/MX25L1673E" \ + -r backup.rom +$ sudo flashrom \ + -p internal \ + -c "MX25L1605D/MX25L1608D/MX25L1673E" \ + --ifd -i bios \ + -w coreboot.rom +``` + +```eval_rst +In addition to the information here, please see the +:doc:`../../flash_tutorial/index`. +``` + +### External flashing + +The SPI flash chip on this board can be flashed externally through the +SPI_ROM1 header while the board is off and disconnected from power. There +seems to be a diode that prevents the external programmer from powering the +whole board. + +The signal assigment on the header is identical to the pinout of the flash +chip. The pinout diagram below is valid when the PCI slots are on the left +and the CPU is on the right. Note that HOLD# and WP# must be pulled high +(to VCC) to be able to flash the chip. + + +---+---+ + SPI_CSn <- | x | x | -> VCC + +---+---+ + SPI_MISO <- | x | x | -> HOLDn + +---+---+ + WPn <- | x | x | -> SPI_CLK + +---+---+ + GND <- | x | x | -> SPI_MOSI + +---+---+ + +## Intel Management Engine + +The Intel Management Engine (ME) can be disabled by setting the ME_DISABLE +jumper on the board. It pulls GPIO33 on the ICH10 low, causing the "Flash +Descriptor Security Override Strap" to be set. This disables the ME and also +disables any read/write restrictions to the flash chip that may be set in the +Intel Flash Descriptor (IFD) (none on this board). Note that changing this +jumper only comes into effect when starting the board from a shutdown or +suspend state, not during normal operation. + +To completely remove the ME blob from the flash image and to decrease the size +of the ME region, thus increasing the size of the BIOS region, `me_cleaner` can +be used with the `-t`, `-r` and `-S` options. + +## Fan control + +There are two fan connectors that can be controlled individually. CPU_FAN +can only control a fan by a PWM signal and SYS_FAN only by voltage. See +the mainboard's `devicetree.cb` file for how coreboot configures the Super +I/O to control the fans. + +## Variants + +Various similar mainboards exist, like the Acer Q45T-AM. During a discussion +in #coreboot on IRC, ECS was suspected to be the original designer of this +series of mainboards. They have similar models such as the ECS G43T-WM. diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index fc602de..67af86f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -6,6 +6,10 @@ - [X210](51nb/x210.md) +## Acer + +- [G43T-AM3](acer/g43t-am3.md) + ## AMD - [padmelon](amd/padmelon/padmelon.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/56838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e296b3efbff0260f32badc699f1062f9885fa53 Gerrit-Change-Number: 56838 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for ...
by Felix Held (Code Review) 26 Dec '21

26 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60031 ) Change subject: Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"" ...................................................................... Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"" This reverts commit a4dddfc3a3a48727ebcec727a0b1fd87eb4c14ad. Reason for revert: Ready to land FSP 2471.02 Change-Id: I2d858edee2eb24506c3e55a1cb808a1ccbd58da2 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60031 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 8 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Ronak Kanabar: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 271e01c..191ef27 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -3164,7 +3164,7 @@ /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved45[104]; + UINT8 Reserved45[136]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3183,11 +3183,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0B10 +/** Offset 0x0B30 **/ - UINT8 UnusedUpdSpace31[6]; + UINT8 UnusedUpdSpace34[6]; -/** Offset 0x0B16 +/** Offset 0x0B36 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index ddf6ca8..a73fe59 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -3380,8 +3380,7 @@ UINT8 ProcHotLock; /** Offset 0x0CF3 - Configuration for boot TDP selection - Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate + Deprecated. Move to premem. **/ UINT8 ConfigTdpLevel; @@ -3869,7 +3868,7 @@ /** Offset 0x0FD5 - Reserved **/ - UINT8 Reserved56[19]; + UINT8 Reserved56[123]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3888,11 +3887,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0FE8 +/** Offset 0x1050 **/ UINT8 UnusedUpdSpace42[6]; -/** Offset 0x0FEE +/** Offset 0x1056 **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/60031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d858edee2eb24506c3e55a1cb808a1ccbd58da2 Gerrit-Change-Number: 60031 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: update telemetry value
by Felix Held (Code Review) 26 Dec '21

26 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60321 ) Change subject: mb/google/guybrush/var/dewatt: update telemetry value ...................................................................... mb/google/guybrush/var/dewatt: update telemetry value AMD SDLE testing had been done and apply the following telemetry settings for dewatt: vdd scale: 95359 vdd offset: 449 soc scale: 31481 soc offset: 193 BUG=b:211566312 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I597a51ca599eff2abc9640aba5f3c804a686f057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60321 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Kenneth Chan: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index f3fd0e6..5366d68 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -13,10 +13,10 @@ register "thermctl_limit_degreeC" = "100" #Update values based on final stardust SDLE test report. - register "telemetry_vddcrvddfull_scale_current_mA" = "94648" #mA - register "telemetry_vddcrvddoffset" = "785" - register "telemetry_vddcrsocfull_scale_current_mA" = "30314" #mA - register "telemetry_vddcrsocoffset" = "560" + register "telemetry_vddcrvddfull_scale_current_mA" = "95359" #mA + register "telemetry_vddcrvddoffset" = "449" + register "telemetry_vddcrsocfull_scale_current_mA" = "31481" #mA + register "telemetry_vddcrsocoffset" = "193" #USB 2.0 phy config register "usb_phy" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/60321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I597a51ca599eff2abc9640aba5f3c804a686f057 Gerrit-Change-Number: 60321 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/types.h: #include <limits.h>
by Felix Held (Code Review) 26 Dec '21

26 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55320 ) Change subject: include/types.h: #include <limits.h> ...................................................................... include/types.h: #include <limits.h> It makes sense to provide limits.h via the types.h header. Change-Id: I3ba189b998644c68068b85f25b11cff4d70c037d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55320 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/types.h 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Felix Held: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/include/types.h b/src/include/types.h index cbdb67a..8724d4b 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -5,6 +5,7 @@ /* types.h is supposed to provide the standard headers defined in here: */ #include <commonlib/bsd/cb_err.h> +#include <limits.h> #include <stdbool.h> #include <stdint.h> #include <stddef.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/55320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba189b998644c68068b85f25b11cff4d70c037d Gerrit-Change-Number: 55320 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Make more brya variants to choose eNEM for CAR
by Subrata Banik (Code Review) 26 Dec '21

26 Dec '21

Attention is currently required from: Felix Singer, David Wu, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60377 ) Change subject: mb/google/brya: Make more brya variants to choose eNEM for CAR ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60377/comment/5526680e_78c7e33e PS2, Line 7: Make more brya variants to choose eNEM for CAR > How about: […] This is good suggestion Felix, but I will keep this patch open for one more week to see if any more brya variants are migrating from ES to QS, if not then I will remain the commit msg and call out only "gimble". WDYT about this plan ? -- To view, visit https://review.coreboot.org/c/coreboot/+/60377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5734606e58410545a5f5421837080680664707f Gerrit-Change-Number: 60377 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: David Wu <david_wu(a)quantatw.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 26 Dec 2021 07:26:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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coreboot-gerrit December 2021