coreboot-gerrit December 2021

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Change in coreboot[master]: soc/mediatek/mt8186: Add devapc basic drivers
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60317 ) Change subject: soc/mediatek/mt8186: Add devapc basic drivers ...................................................................... Patch Set 6: (4 comments) File src/soc/mediatek/mt8186/devapc.c: https://review.coreboot.org/c/coreboot/+/60317/comment/8ed42308_e45df282 PS5, Line 6: static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = { > How did you create this? Copied from datasheet? add information at the beginning of this file. https://review.coreboot.org/c/coreboot/+/60317/comment/cf3fde74_b444199c PS5, Line 1252: int > unsigned int Done https://review.coreboot.org/c/coreboot/+/60317/comment/5012af72_21434786 PS5, Line 1306: int > unsigned int Done File src/soc/mediatek/mt8186/include/soc/devapc.h: https://review.coreboot.org/c/coreboot/+/60317/comment/160b16cc_1eabbe0b PS5, Line 17: AO_APC_CON = 0x0F00, > Please add the datasheet name, revision and section, where you got the offsets from. add information at the beginning of this file. -- To view, visit https://review.coreboot.org/c/coreboot/+/60317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Gerrit-Change-Number: 60317 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 02:40:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60316 ) Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60316/comment/32fc43f2_bee70964 PS4, Line 8: > Please describe the problem at hand. Done https://review.coreboot.org/c/coreboot/+/60316/comment/bf4995a9_78eb7150 PS4, Line 9: However the BootROM : has configured only half of L2/L3 cache as SRAM. > Is that a bug? Can the BootROM be fixed? No, it's not a bug. BootRom configures this setting to use this memory as half for data cache and half for SRAM. It's almost impossible to change this setting from BootRom because it's not unchangeable when the SoCs are taped out. -- To view, visit https://review.coreboot.org/c/coreboot/+/60316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 Gerrit-Change-Number: 60316 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 02:39:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add devapc basic drivers
by build bot (Jenkins) (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60317 ) Change subject: soc/mediatek/mt8186: Add devapc basic drivers ...................................................................... Patch Set 6: (9 comments) File src/soc/mediatek/mt8186/include/soc/devapc.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/462a2a74_7c598d8b PS6, Line 70: #define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/1a65fcfa_626dcf3c PS6, Line 75: #define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/5a4918a3_6d2513ef PS6, Line 83: #define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/420b1865_8650241c PS6, Line 97: #define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/bc2a2b72_3c8fdf93 PS6, Line 98: #define FORBIDDEN4 FORBIDDEN3, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/719b6c64_a3ca554a PS6, Line 99: #define FORBIDDEN5 FORBIDDEN4, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/3bd2f838_5babbe13 PS6, Line 100: #define FORBIDDEN6 FORBIDDEN5, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/66dc42b7_7b89d884 PS6, Line 101: #define FORBIDDEN7 FORBIDDEN6, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136263): https://review.coreboot.org/c/coreboot/+/60317/comment/18662c23_76e7b3c8 PS6, Line 103: #define NO_PROTECTION4 NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/60317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Gerrit-Change-Number: 60317 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 02:39:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add DRAM full calibration support
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60318 ) Change subject: soc/mediatek/mt8186: Add DRAM full calibration support ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7 Gerrit-Change-Number: 60318 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 02:38:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Enable VRF12 software control for MT6366
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60340 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: Enable VRF12 software control for MT6366 ...................................................................... soc/mediatek/mt8186: Enable VRF12 software control for MT6366 PS8640 is a low power MIPI-to-eDP video format converter. VRF12 does not provide power to PS8640 on krabby. In original patch, VRF12 is not used, and is set to hardware control for low power. We change the setting to remove hardware control. Therefore, if we want to control VRF12 by software, we can control it directly. BUG=b:210806060 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549 --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/60340/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549 Gerrit-Change-Number: 60340 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add devapc basic drivers
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60317 to look at the new patch set (#6). Change subject: soc/mediatek/mt8186: Add devapc basic drivers ...................................................................... soc/mediatek/mt8186: Add devapc basic drivers Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set default permission. BUG=b:202871018 TEST=build pass Signed-off-by: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/devapc.c A src/soc/mediatek/mt8186/include/soc/devapc.h M src/soc/mediatek/mt8186/soc.c 4 files changed, 1,456 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/60317/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/60317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Gerrit-Change-Number: 60317 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60316 to look at the new patch set (#5). Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C ...................................................................... soc/mediatek/mt8186: Adjust usage of SRAM L2C We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before DRAM calibration. When we check cbmem, we found the content of this memory is unreadable. The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM has configured only half of L2/L3 cache as SRAM. Therefore, decrease the size of each SRAM region to fit into the first half of the cache. BUG=b:207725851 TEST=Bootblock log looked good in `cbmem -c` Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 --- M src/soc/mediatek/mt8186/include/soc/memlayout.ld 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60316/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/60316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 Gerrit-Change-Number: 60316 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/taniks:Correct usb{23}_port_number fields
by Joey Peng (Code Review) 27 Dec '21

27 Dec '21

Joey Peng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60333 ) Change subject: mb/google/brya/var/taniks:Correct usb{23}_port_number fields ...................................................................... Abandoned https://review.coreboot.org/c/coreboot/+/60329 has fixed this issue -- To view, visit https://review.coreboot.org/c/coreboot/+/60333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcf107df90dc598fd31485fa0299e890ee7a9ccd Gerrit-Change-Number: 60333 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brya/var/gimble: Decrease touchscreen T3 timing to 200ms
by Scott Chao (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60270 ) Change subject: mb/google/brya/var/gimble: Decrease touchscreen T3 timing to 200ms ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60270/comment/f388e70b_fddbeed7 PS1, Line 7: variants > var Done https://review.coreboot.org/c/coreboot/+/60270/comment/f36c7a03_6e4bd1d3 PS1, Line 7: modify > Decrease Done https://review.coreboot.org/c/coreboot/+/60270/comment/5f8d6130_86be301d PS1, Line 9: will failed > fails Done Patchset: PS1: > Sounds like a bad idea to violate the spec. Got Elan's feedback as below. In Elan's spec, the host should NOT send commands until 300ms after RESETB is pulled high. As WISTRON mention at #4, the limitation of reset_delay_ms must not lower than 150ms. we think 200ms is ok for reset_delay. -- To view, visit https://review.coreboot.org/c/coreboot/+/60270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bb4eda09686cb59b6e19c741aa2b78d84332d2a Gerrit-Change-Number: 60270 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 00:23:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Decrease touchscreen T3 timing to 200ms
by Scott Chao (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Tim Wawrzynczak, Scott Chao. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60270 ) Change subject: mb/google/brya/var/gimble: Decrease touchscreen T3 timing to 200ms ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/60270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bb4eda09686cb59b6e19c741aa2b78d84332d2a Gerrit-Change-Number: 60270 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 00:22:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021