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Change subject: soc/intel/jasperlake: Add CdClock frequency config
......................................................................
Patch Set 18:
(1 comment)
File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/60009/comment/dd04c618_39083b5c
PS17, Line 212: params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
> Updated fsp header in patchset#18, and the inside of fsp related change will release later.
Can you please update commit msg saying you have updated the FSP-S UPD help text to align the code behaviour with the UPD for CdClock.
Hopefully next time someone updating the JSL FSP headers shouldn't override this to default as you are not fixing it at source yet ?
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Change subject: mb/google/cherry: add configuration for dojo
......................................................................
Patch Set 3: Code-Review+1
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Change subject: ec/purism/librem-ec: Use Printf() for debug prints
......................................................................
Set Ready For Review
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Change subject: mb/google/cherry: add configuration for dojo
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/cherry/Kconfig:
https://review.coreboot.org/c/coreboot/+/60313/comment/93370795_29ad850e
PS2, Line 66: default y if BOARD_GOOGLE_CHERRY || BOARD_GOOGLE_DOJO || BOARD_GOOGLE_TOMATO
> if all boards so far do use rt1019, can we change these to […]
Done
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Hello Hung-Te Lin, build bot (Jenkins), Chen-Tsung Hsieh, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60313
to look at the new patch set (#3).
Change subject: mb/google/cherry: add configuration for dojo
......................................................................
mb/google/cherry: add configuration for dojo
BUG=b:211528578
TEST=emerge-cherry coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
Change-Id: I3bd9803b4e47882df9fe351229478e4cb1630363
---
M src/mainboard/google/cherry/Kconfig
M src/mainboard/google/cherry/Kconfig.name
2 files changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/60313/3
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David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60388 )
Change subject: mb/google/brya/var/kano: disabled autonomous GPIO power management
......................................................................
mb/google/brya/var/kano: disabled autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:201266532
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Change-Id: I9607af42a00c1b5f38c6e4e0effdeeaba18af5ff
---
M src/mainboard/google/brya/variants/kano/overridetree.cb
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/60388/1
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index a7e4271..848100e 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -15,6 +15,17 @@
chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled"
+ # This disabled autonomous GPIO power management, otherwise
+ # old cr50 FW only supports short pulses; need to clarify
+ # the minimum PCH IRQ pulse width with Intel, b/180111628
+ register "gpio_override_pm" = "1"
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
+ register "gpio_pm[COMM_4]" = "0"
+ register "gpio_pm[COMM_5]" = "0"
+
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_D"
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Change subject: soc/mediatek/mt8186: Add DRAM full calibration support
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS7:
> done
I have separate original patch into three patches:
https://review.coreboot.org/c/coreboot/+/60385https://review.coreboot.org/c/coreboot/+/60318https://review.coreboot.org/c/coreboot/+/60386
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Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60316/comment/5e0dc319_999bb450
PS4, Line 9: However the BootROM
: has configured only half of L2/L3 cache as SRAM.
> No, it's not a bug. […]
Sorry for error type:
because "it's unchangeable" when the SoCs are taped out.
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