coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Simon Yang (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Angel Pons, Kane Chen, Patrick Rudolph. Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... Patch Set 21: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60009/comment/2e5a5423_d04c4cba PS19, Line 15: The header file FspsUpd.h also updated the help text to match the : correct CdClock definition. > Yes, it's ongoing. I will keep tracking this internally. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 21 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 07:53:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Simon Yang <simon1.yang(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Simon Yang (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Angel Pons, Kane Chen, Patrick Rudolph. Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... Patch Set 20: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60009/comment/bf5ab224_da15e0c3 PS19, Line 15: The header file FspsUpd.h also updated the help text to match the : correct CdClock definition. > Maybe: […] Yes, it's ongoing. I will keep tracking this internally. File src/soc/intel/jasperlake/chip.h: https://review.coreboot.org/c/coreboot/+/60009/comment/75c08199_63fc405f PS19, Line 408: Cdclock > CdClock Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 20 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 07:51:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Enable VRF12 software control for MT6366
by Yu-Ping Wu (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60340 ) Change subject: soc/mediatek/mt8186: Enable VRF12 software control for MT6366 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549 Gerrit-Change-Number: 60340 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 07:51:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Simon Yang (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Tim Wawrzynczak, Ren Kuo, Angel Pons, Kane Chen, Patrick Rudolph. Hello build bot (Jenkins), Jamie Chen, Subrata Banik, Henry Sun, Tim Wawrzynczak, Angel Pons, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60009 to look at the new patch set (#21). Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... soc/intel/jasperlake: Add CdClock frequency config Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 3 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 21 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add devapc basic drivers
by Yu-Ping Wu (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60317 ) Change subject: soc/mediatek/mt8186: Add devapc basic drivers ...................................................................... Patch Set 6: (2 comments) File src/soc/mediatek/mt8186/devapc.c: https://review.coreboot.org/c/coreboot/+/60317/comment/b3feb887_446122cb PS6, Line 1283: Remove blank line File src/soc/mediatek/mt8186/include/soc/devapc.h: https://review.coreboot.org/c/coreboot/+/60317/comment/b8ff64aa_87cfda8f PS6, Line 70: #define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3) \ : (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ : (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, : : #define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ : PERM_ATTR6, PERM_ATTR7) \ : DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3) \ : DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ : PERM_ATTR6, PERM_ATTR7) : : #define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ : PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ : PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ : PERM_ATTR14, PERM_ATTR15) \ : DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3, \ : PERM_ATTR4, PERM_ATTR5, \ : PERM_ATTR6, PERM_ATTR7) \ : DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ : PERM_ATTR10, PERM_ATTR11, \ : PERM_ATTR12, PERM_ATTR13, \ : PERM_ATTR14, PERM_ATTR15) : : #define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN : #define FORBIDDEN4 FORBIDDEN3, FORBIDDEN : #define FORBIDDEN5 FORBIDDEN4, FORBIDDEN : #define FORBIDDEN6 FORBIDDEN5, FORBIDDEN : #define FORBIDDEN7 FORBIDDEN6, FORBIDDEN : : #define NO_PROTECTION4 NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION Can we move these to a common header file (to be shared with mt8195)? -- To view, visit https://review.coreboot.org/c/coreboot/+/60317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Gerrit-Change-Number: 60317 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 07:50:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Simon Yang (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Tim Wawrzynczak, Ren Kuo, Simon Yang, Angel Pons, Kane Chen, Patrick Rudolph. Hello build bot (Jenkins), Jamie Chen, Subrata Banik, Henry Sun, Tim Wawrzynczak, Angel Pons, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60009 to look at the new patch set (#20). Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... soc/intel/jasperlake: Add CdClock frequency config Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 3 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 20 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add header files to support DRAM calibration
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60385 ) Change subject: soc/mediatek/mt8186: Add header files to support DRAM calibration ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8186/include/soc/dramc_param.h: https://review.coreboot.org/c/coreboot/+/60385/comment/211a4ebe_4096838a PS2, Line 59: struct dramc_param_header { > Do we want to use the version in CL:3257390 (with dramc_param_common. […] I think we can upstream this version first, which is used for DRAM full calibration. CL:3257390 is used for fast-k. -- To view, visit https://review.coreboot.org/c/coreboot/+/60385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387 Gerrit-Change-Number: 60385 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 07:45:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Prevent passing NULL MIPI commands
by Paul Menzel (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60392 ) Change subject: soc/mediatek: Prevent passing NULL MIPI commands ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60392/comment/c7a62f0d_75f74446 PS1, Line 9: (before CB:56965) Please also add the git commit hash (and commit message summary), as that is what git operates with. -- To view, visit https://review.coreboot.org/c/coreboot/+/60392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8196e3b135da273325e2e121523abb7fb230a49c Gerrit-Change-Number: 60392 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 07:43:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
by Paul Menzel (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Nico Huber, Henry Sun, Ren Kuo, Angel Pons, Kane Chen, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60301/comment/90bb62f9_691d807e PS9, Line 12: per Intel recommendation What team or document recommended this? -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 9 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 07:42:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C
by Yu-Ping Wu (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60316 ) Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 Gerrit-Change-Number: 60316 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 07:42:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021