coreboot-gerrit December 2021

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Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C
by Hung-Te Lin (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Rex-BC Chen, Paul Menzel. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60316 ) Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60316/comment/d5e3d4da_d44e8bb6 PS4, Line 9: However the BootROM : has configured only half of L2/L3 cache as SRAM. > No, it's not a bug. […] "unchangeable" does not mean it's not a bug - it can still be a silicon bug. The key is that we still need some space for cache, otherwise the system won't be able to run. One thing can be discussed is if we can configure the cache smaller, for example only 1/4 (256Kb). -- To view, visit https://review.coreboot.org/c/coreboot/+/60316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 Gerrit-Change-Number: 60316 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 08:53:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: Initialize kingler display
by Hung-Te Lin (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60398 ) Change subject: mb/google/corsola: Initialize kingler display ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/corsola/display.c: https://review.coreboot.org/c/coreboot/+/60398/comment/1ddc52fe_9dec7a2b PS1, Line 110: (void) no need to add this (void) ? -- To view, visit https://review.coreboot.org/c/coreboot/+/60398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91 Gerrit-Change-Number: 60398 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 08:53:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Prevent passing NULL MIPI commands
by Hung-Te Lin (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60392 ) Change subject: soc/mediatek: Prevent passing NULL MIPI commands ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8196e3b135da273325e2e121523abb7fb230a49c Gerrit-Change-Number: 60392 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 08:47:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add header files to support DRAM calibration
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ryan Chuang, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60385 ) Change subject: soc/mediatek/mt8186: Add header files to support DRAM calibration ...................................................................... Patch Set 3: (3 comments) Commit Message: PS2: > IMO CB:60318 could be merged into this patch. suggestion from: https://review.coreboot.org/c/coreboot/+/60318/7..10//COMMIT_MSG#b10 File src/soc/mediatek/mt8186/include/soc/dramc_param.h: https://review.coreboot.org/c/coreboot/+/60385/comment/8827d330_21a2d2f7 PS2, Line 59: struct dramc_param_header { > Okay, but please add the 'config' field here first. Otherwise there will be incompatible changes. Done https://review.coreboot.org/c/coreboot/+/60385/comment/46c1497b_adb06b32 PS2, Line 149: int validate_dramc_param(const void *blob); : int is_valid_dramc_param(const void *blob); > These 2 don't exist in common/dramc_param.c, and they are not called either. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387 Gerrit-Change-Number: 60385 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 08:30:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add devapc basic drivers
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60317 ) Change subject: soc/mediatek/mt8186: Add devapc basic drivers ...................................................................... Patch Set 7: (2 comments) File src/soc/mediatek/mt8186/devapc.c: https://review.coreboot.org/c/coreboot/+/60317/comment/af17123a_d9fa9ca4 PS6, Line 1283: > Remove blank line Done File src/soc/mediatek/mt8186/include/soc/devapc.h: https://review.coreboot.org/c/coreboot/+/60317/comment/c1e973d9_51215f75 PS6, Line 70: #define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3) \ : (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ : (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, : : #define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ : PERM_ATTR6, PERM_ATTR7) \ : DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3) \ : DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ : PERM_ATTR6, PERM_ATTR7) : : #define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ : PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ : PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ : PERM_ATTR14, PERM_ATTR15) \ : DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ : PERM_ATTR2, PERM_ATTR3, \ : PERM_ATTR4, PERM_ATTR5, \ : PERM_ATTR6, PERM_ATTR7) \ : DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ : PERM_ATTR10, PERM_ATTR11, \ : PERM_ATTR12, PERM_ATTR13, \ : PERM_ATTR14, PERM_ATTR15) : : #define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN : #define FORBIDDEN4 FORBIDDEN3, FORBIDDEN : #define FORBIDDEN5 FORBIDDEN4, FORBIDDEN : #define FORBIDDEN6 FORBIDDEN5, FORBIDDEN : #define FORBIDDEN7 FORBIDDEN6, FORBIDDEN : : #define NO_PROTECTION4 NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION > Can we move these to a common header file (to be shared with mt8195)? done see https://review.coreboot.org/c/coreboot/+/60394 -- To view, visit https://review.coreboot.org/c/coreboot/+/60317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Gerrit-Change-Number: 60317 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 08:29:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: Initialize kingler display
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60398 ) Change subject: mb/google/corsola: Initialize kingler display ...................................................................... mb/google/corsola: Initialize kingler display ANX7625 is used on Kingler board as the eDP bridge IC. Enable ANX7625 and configure display in mainboard_init() to support display in firmware screen. BUG=b:209930699 TEST=see fw display on kingler panel Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91 --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Makefile.inc A src/mainboard/google/corsola/display.c A src/mainboard/google/corsola/display.h M src/mainboard/google/corsola/gpio.h M src/mainboard/google/corsola/mainboard.c 6 files changed, 145 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/60398/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index e381502..702c3fc 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -35,6 +35,9 @@ select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_ANALOGIX_ANX7625 config MAINBOARD_DIR string diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index e1e363c..30ee6c1 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -16,6 +16,7 @@ ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-y += chromeos.c +ramstage-y += display.c ramstage-y += mainboard.c ramstage-y += regulator.c ramstage-y += reset.c diff --git a/src/mainboard/google/corsola/display.c b/src/mainboard/google/corsola/display.c new file mode 100644 index 0000000..2dec6df --- /dev/null +++ b/src/mainboard/google/corsola/display.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio_common.h> +#include <soc/i2c.h> +#include <soc/mtcmos.h> + +#include "display.h" +#include "gpio.h" + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_backlight_and_bridge(void) +{ + /* Disable backlight before turning on bridge */ + gpio_output(GPIO_AP_EDP_BKLTEN, 0); + gpio_output(GPIO_BL_PWM_1V8, 0); + gpio_output(GPIO_EN_PP3300_DISP_X, 1); + + /* Turn on bridge */ + gpio_output(GPIO_EDPBRDG_RST_L, 0); + gpio_output(GPIO_EN_PP1000_EDPBRDG, 1); + gpio_output(GPIO_EN_PP1800_EDPBRDG, 1); + gpio_output(GPIO_EN_PP3300_EDPBRDG, 1); + mdelay(14); + gpio_output(GPIO_EDPBRDG_PWREN, 1); + mdelay(10); + gpio_output(GPIO_EDPBRDG_RST_L, 1); +} + +static int anx7625_setup(u8 i2c_bus, struct edid *edid) +{ + if (anx7625_init(i2c_bus) < 0) { + printk(BIOS_ERR, "%s: Can't init ANX7625 bridge\n", __func__); + return -1; + } + if (anx7625_dp_get_edid(i2c_bus, edid) < 0) { + printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); + return -1; + } + return 0; +} + +static int bridge_setup(u8 i2c_bus, struct edid *edid) +{ + if (CONFIG(BOARD_GOOGLE_KINGLER_COMMON)) + return anx7625_setup(i2c_bus, edid); + else + printk(BIOS_ERR, "%s: There is no bridge IC supported\n", __func__); + + return -1; +} + +static int bridge_post_poweron(u8 i2c_bus, struct edid *edid) +{ + if (CONFIG(BOARD_GOOGLE_KINGLER_COMMON)) + return anx7625_dp_start(i2c_bus, edid); + + return 0; +} + +int configure_display(void) +{ + struct edid edid; + const u8 i2c_bus = I2C0; + + printk(BIOS_INFO, "%s: Starting display init\n", __func__); + + configure_backlight_and_bridge(); + mtk_i2c_bus_init(i2c_bus, I2C_SPEED_FAST); + + if (bridge_setup(i2c_bus, &edid) < 0) { + printk(BIOS_ERR, "%s: Failed to set bridge\n", __func__); + return -1; + } + + const char *name = edid.ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, + edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, + edid.mode.refresh); + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + mtk_ddp_init(); + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET); + + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); + return -1; + } + + if (bridge_post_poweron(i2c_bus, &edid) < 0) { + printk(BIOS_ERR, "%s: Failed to post poweron bridge\n", __func__); + return -1; + } + + mtk_ddp_mode_set(&edid); + (void)fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); + + return 0; +} diff --git a/src/mainboard/google/corsola/display.h b/src/mainboard/google/corsola/display.h new file mode 100644 index 0000000..525422b --- /dev/null +++ b/src/mainboard/google/corsola/display.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ + +int configure_display(void); + +#endif diff --git a/src/mainboard/google/corsola/gpio.h b/src/mainboard/google/corsola/gpio.h index c2f789e..8f8fb72 100644 --- a/src/mainboard/google/corsola/gpio.h +++ b/src/mainboard/google/corsola/gpio.h @@ -9,7 +9,6 @@ #define GPIO_BT_WAKE_AP_ODL GPIO(EINT6) #define GPIO_WIFI_INT_ODL GPIO(EINT7) #define GPIO_DPBRDG_INT_ODL GPIO(EINT8) -#define GPIO_EDPBRDG_INT_ODL GPIO(EINT9) #define GPIO_EC_AP_HPD_OD GPIO(EINT10) #define GPIO_TCHPAD_INT_ODL GPIO(EINT11) #define GPIO_TCHSCR_INT_1V8_ODL GPIO(EINT12) @@ -27,6 +26,17 @@ #define GPIO_EN_SPK GPIO(PERIPHERAL_EN3) #define GPIO_BEEP_ON GPIO(PERIPHERAL_EN4) +/* GPIOs for display */ +#define GPIO_AP_EDP_BKLTEN GPIO(PERIPHERAL_EN5) +#define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) +#define GPIO_EN_PP3300_DISP_X GPIO(PERIPHERAL_EN6) +#define GPIO_EDPBRDG_RST_L GPIO(LCM_RST) +#define GPIO_EN_PP1000_EDPBRDG GPIO(ANT_SEL0) +#define GPIO_EN_PP1800_EDPBRDG GPIO(ANT_SEL1) +#define GPIO_EN_PP3300_EDPBRDG GPIO(ANT_SEL2) +#define GPIO_EDPBRDG_INT_ODL GPIO(EINT9) +#define GPIO_EDPBRDG_PWREN GPIO(DSI_TE) + void setup_chromeos_gpios(void); #endif diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index fa4aa18..910d8d6 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bl31.h> +#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/msdc.h> #include <soc/spm.h> #include <soc/usb.h> +#include "display.h" #include "gpio.h" #include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> @@ -37,6 +39,13 @@ printk(BIOS_ERR, "spm init failed, system suspend may not work\n"); register_reset_to_bl31(); + + if (display_init_required()) { + if (configure_display() < 0) + printk(BIOS_ERR, "%s: Failed to init display\n", __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display init\n", __func__); + } } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/60398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91 Gerrit-Change-Number: 60398 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Add DSI driver
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60397 ) Change subject: soc/mediatek/mt8186: Add DSI driver ...................................................................... soc/mediatek/mt8186: Add DSI driver Enable DSI for display. BUG=b:209930699 TEST=Firmware display looked good Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16 --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/include/soc/dsi.h 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/60397/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index dd7541f..f99bd47 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c +ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8186/include/soc/dsi.h b/src/soc/mediatek/mt8186/include/soc/dsi.h new file mode 100644 index 0000000..778cb44 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dsi.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8186_DSI_H +#define SOC_MEDIATEK_MT8186_DSI_H + +#include <soc/dsi_common.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/60397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16 Gerrit-Change-Number: 60397 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Add DDP driver
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60396 ) Change subject: soc/mediatek/mt8186: Add DDP driver ...................................................................... soc/mediatek/mt8186: Add DDP driver Add DDP (display controller) driver that supports main path to eDP panel. The output goes to display interface DSI. BUG=b:209930699 TEST=saw firmware display Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1 --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/ddp.c M src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/ddp.h 4 files changed, 427 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/60396/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index c940d37..dd7541f 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -44,6 +44,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += ../common/auxadc.c +ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c new file mode 100644 index 0000000..53eb75a --- /dev/null +++ b/src/soc/mediatek/mt8186/ddp.c @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <edid.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +static void disp_config_main_path_connection(void) +{ + /* + * Main path: + * OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA-> + * POSTMASK0->DITHER->DSI0 + */ + SET32_BITFIELDS(&mmsys_cfg->disp_ovl0_mout_en, + DISP_OVL0_MOUT_EN, DISP_OVL0_MOUT_TO_RDMA0); + SET32_BITFIELDS(&mmsys_cfg->disp_rdma0_sel_in, + DISP_RDMA0_SEL_IN, DISP_RDMA0_FROM_OVL0); + SET32_BITFIELDS(&mmsys_cfg->mmsys_ovl_con, + DISP_MMSYS_OVL0_CON, DISP_OVL0_GO_BLEND); + SET32_BITFIELDS(&mmsys_cfg->disp_rdma0_sout_sel, + DISP_RDMA0_SOUT_SEL, DISP_RDMA0_SOUT_TO_COLOR0); + SET32_BITFIELDS(&mmsys_cfg->disp_dither0_mout_en, + DISP_DITHER0_MOUT_EN, DISP_DITHER0_MOUT_TO_DSI0); + SET32_BITFIELDS(&mmsys_cfg->disp_dsi0_sel_in, + DISP_DSI0_SEL_IN, DISP_DSI0_FROM_DITHER0); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_layer_smi_id_en(u32 idx) +{ + SET32_BITFIELDS(&disp_ovl[idx]->datapath_con, + SMI_ID_EN, SMI_ID_EN_VAL); +} + +static void ccorr_config(u32 width, u32 height) +{ + struct disp_ccorr_regs *const regs = disp_ccorr; + + write32(&regs->size, width << 16 | height); + + /* Disable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, 0); + SET32_BITFIELDS(&regs->cfg, PQ_CFG_ENGINE_EN, PQ_ENGINE_EN); + + write32(&regs->en, PQ_EN); +} + +static void aal_config(u32 width, u32 height) +{ + struct disp_aal_regs *const regs = disp_aal; + + write32(&regs->size, width << 16 | height); + write32(&regs->output_size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + SET32_BITFIELDS(&regs->cfg, PQ_CFG_ENGINE_EN, 0); + + write32(&regs->en, PQ_EN); +} + +static void gamma_config(u32 width, u32 height) +{ + struct disp_gamma_regs *const regs = disp_gamma; + + write32(&regs->size, width << 16 | height); + + /* Disable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, 0); + + write32(&regs->en, PQ_EN); +} + +static void postmask_config(u32 width, u32 height) +{ + struct disp_postmask_regs *const regs = disp_postmask; + + write32(&regs->size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void dither_config(u32 width, u32 height) +{ + struct disp_dither_regs *const regs = disp_dither; + + write32(&regs->size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 pixel_clk = width * height * vrefresh; + + /* One ovl in main path */ + ovl_set_roi(0, width, height, 0xff0000ff); + ovl_layer_smi_id_en(0); + rdma_config(width, height, pixel_clk, 5 * KiB); + color_start(width, height); + ccorr_config(width, height); + aal_config(width, height); + gamma_config(width, height); + postmask_config(width, height); + dither_config(width, height); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + + /* Turn off M4U port. */ + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + printk(BIOS_INFO, "%s: display resolution: %ux%u@%u bpp %u\n", + __func__, width, height, vrefresh, bpp); + + if (!vrefresh) { + vrefresh = 60; + printk(BIOS_INFO, "%s: invalid vrefresh; setting to %u\n", + __func__, vrefresh); + } + + main_disp_path_setup(width, height, vrefresh); + rdma_start(); + ovl_layer_config(fmt, bpp, width, height); +} diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index adb1d59..c90e0cd 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -75,8 +75,19 @@ EFUSEC_BASE = IO_PHYS + 0x01CB0000, MIPITX_BASE = IO_PHYS + 0x01CC0000, MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_MUTEX_BASE = IO_PHYS + 0x04001000, SMI_BASE = IO_PHYS + 0x04002000, SMI_LARB0 = IO_PHYS + 0x04003000, + DISP_OVL0_BASE = IO_PHYS + 0x04005000, + DISP_OVL1_BASE = IO_PHYS + 0x04006000, + DISP_RDMA0_BASE = IO_PHYS + 0x04007000, + DISP_COLOR0_BASE = IO_PHYS + 0x04009000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400B000, + DISP_AAL0_BASE = IO_PHYS + 0x0400C000, + DISP_GAMMA0_BASE = IO_PHYS + 0x0400D000, + DISP_POSTMASK0_BASE = IO_PHYS + 0x0400E000, + DISP_DITHER0_BASE = IO_PHYS + 0x0400F000, DSI0_BASE = IO_PHYS + 0x04013000, }; #endif diff --git a/src/soc/mediatek/mt8186/include/soc/ddp.h b/src/soc/mediatek/mt8186/include/soc/ddp.h new file mode 100644 index 0000000..b349367 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/ddp.h @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8186_DDP_H +#define SOC_MEDIATEK_MT8186_DDP_H + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/ddp_common.h> +#include <types.h> + +#define SMI_LARB_PORT_L0_OVL_RDMA0 0x388 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10c; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11c[33]; /* 0x11C */ + u32 mmsys_cg_con2; /* 0x1A0 */ + u32 mmsys_cg_set2; /* 0x1A4 */ + u32 mmsys_cg_clr2; /* 0x1A8 */ + u32 reserved_0x1ac[853]; /* 0x1AC */ + u32 reserved_0xf00; /* 0xF00 */ + u32 mmsys_ovl_con; /* 0xF04 */ + u32 reserved_0xf08; /* 0xF08 */ + u32 disp_rdma0_sout_sel; /* 0xF0C */ + u32 reserved_0xf10; /* 0xF10 */ + u32 disp_ovl0_2l_mout_en; /* 0xF14 */ + u32 disp_ovl0_mout_en; /* 0xF18 */ + u32 reserved_0xf1c; /* 0xF1C */ + u32 disp_dither0_mout_en; /* 0xF20 */ + u32 reserved_0xf24; /* 0xF24 */ + u32 disp_rdma0_sel_in; /* 0xF28 */ + u32 reserved_0xf2c; /* 0xF2C */ + u32 disp_dsi0_sel_in; /* 0xF30 */ + u32 reserved_0xf34[2]; /* 0xF34 */ + u32 disp_rdma1_mout_en; /* 0xF3C */ + u32 disp_rdma1_sel_in; /* 0xF40 */ + u32 disp_dpi0_sel_in; /* 0xF44 */ +}; +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); +check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0); +check_member(mmsys_cfg_regs, mmsys_ovl_con, 0xF04); +check_member(mmsys_cfg_regs, disp_rdma0_sout_sel, 0xF0C); +check_member(mmsys_cfg_regs, disp_ovl0_mout_en, 0xF18); +check_member(mmsys_cfg_regs, disp_dither0_mout_en, 0xF20); +check_member(mmsys_cfg_regs, disp_rdma0_sel_in, 0xF28); +check_member(mmsys_cfg_regs, disp_dsi0_sel_in, 0xF30); + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[16]; +}; + +struct disp_ccorr_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[27]; + u32 shadow; +}; +check_member(disp_ccorr_regs, shadow, 0xA0); + +struct disp_gamma_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_gamma_regs, size, 0x30); + +struct disp_aal_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[47]; + u32 shadow; + u32 reserved3[249]; + u32 output_size; +}; +check_member(disp_aal_regs, shadow, 0xF0); +check_member(disp_aal_regs, output_size, 0x4D8); + +struct disp_postmask_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 reserved0[4]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_postmask_regs, size, 0x30); + +struct disp_dither_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[51]; + u32 disp_dither_0; +}; +check_member(disp_dither_regs, disp_dither_0, 0x100); + +/* + * DISP_REG_CONFIG_MMSYS_CG_CON0 + * Configures free-run clock gating 0 + * 0: Enable clock + * 1: Clock gating + */ +enum { + CG_CON0_DISP_MUTEX0 = BIT(0), + CG_CON0_APB_MM_BUS = BIT(1), + CG_CON0_DISP_OVL0 = BIT(2), + CG_CON0_DISP_RDMA0 = BIT(3), + CG_CON0_DISP_OVL0_2L = BIT(4), + CG_CON0_DISP_WDMA0 = BIT(5), + CG_CON0_DISP_RSZ0 = BIT(7), + CG_CON0_DISP_AAL0 = BIT(8), + CG_CON0_DISP_CCORR0 = BIT(9), + CG_CON0_DISP_COLOR0 = BIT(10), + CG_CON0_SMI_INFRA = BIT(11), + CG_CON0_DISP_GAMMA0 = BIT(13), + CG_CON0_DISP_POSTMASK0 = BIT(14), + CG_CON0_DISP_DITHER0 = BIT(16), + CG_CON0_SMI_COMMON = BIT(17), + CG_CON0_DISP_DSI0 = BIT(19), + CG_CON0_DISP_FAKE_ENG0 = BIT(20), + CG_CON0_DISP_FAKE_ENG1 = BIT(21), + CG_CON0_SMI_GALS = BIT(22), + CG_CON0_SMI_IOMMU = BIT(24), + CG_CON0_DISP_ALL = CG_CON0_DISP_MUTEX0 | + CG_CON0_APB_MM_BUS | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_SMI_INFRA | + CG_CON0_DISP_GAMMA0 | + CG_CON0_DISP_POSTMASK0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_SMI_COMMON | + CG_CON0_DISP_DSI0 | + CG_CON0_SMI_GALS | + CG_CON0_SMI_IOMMU, + CG_CON0_ALL = 0xFFFFFFFF, +}; + +enum { + CG_CON2_DSI0_DSI_CK_DOMAIN = BIT(0), + CG_CON2_DISP_26M = BIT(10), + CG_CON2_DISP_ALL = CG_CON2_DSI0_DSI_CK_DOMAIN | + CG_CON2_DISP_26M, + CG_CON2_ALL = 0xFFFFFFFF, +}; + +DEFINE_BITFIELD(DISP_OVL0_MOUT_EN, 3, 0) +DEFINE_BITFIELD(DISP_RDMA0_SEL_IN, 3, 0) +DEFINE_BITFIELD(DISP_MMSYS_OVL0_CON, 1, 0) +DEFINE_BITFIELD(DISP_RDMA0_SOUT_SEL, 3, 0) +DEFINE_BITFIELD(DISP_DITHER0_MOUT_EN, 3, 0) +DEFINE_BITFIELD(DISP_DSI0_SEL_IN, 3, 0) + +DEFINE_BIT(SMI_ID_EN, 0) +DEFINE_BIT(PQ_CFG_RELAY_MODE, 0) +DEFINE_BIT(PQ_CFG_ENGINE_EN, 1) + +#define DISP_OVL0_MOUT_TO_RDMA0 BIT(0) +#define DISP_RDMA0_FROM_OVL0 0 +#define DISP_OVL0_GO_BLEND BIT(0) +#define DISP_RDMA0_SOUT_TO_COLOR0 1 +#define DISP_DITHER0_MOUT_TO_DSI0 BIT(0) +#define DISP_DSI0_FROM_DITHER0 1 + +#define SMI_ID_EN_VAL BIT(0) + +enum { + MUTEX_MOD_DISP_OVL0 = BIT(0), + MUTEX_MOD_DISP_RDMA0 = BIT(2), + MUTEX_MOD_DISP_COLOR0 = BIT(4), + MUTEX_MOD_DISP_CCORR0 = BIT(5), + MUTEX_MOD_DISP_AAL0 = BIT(7), + MUTEX_MOD_DISP_GAMMA0 = BIT(8), + MUTEX_MOD_DISP_POSTMASK0 = BIT(9), + MUTEX_MOD_DISP_DITHER0 = BIT(10), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | + MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | + MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_POSTMASK0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +#define PQ_EN BIT(0) +#define PQ_RELAY_MODE BIT(0) +#define PQ_ENGINE_EN BIT(1) + +static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_BASE; +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; +static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; +static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; +static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; +static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; +static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/60396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1 Gerrit-Change-Number: 60396 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: Add board common config for kingler and krabby
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60395 ) Change subject: mb/google/corsola: Add board common config for kingler and krabby ...................................................................... mb/google/corsola: Add board common config for kingler and krabby Add common configs to help implementing board-specific logic (for example using different eDP bridge IC drivers). BUG=b:209930699 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If775532c1a262f3e8b3f11b24cae555844f2bfec --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/60395/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 193cafd..e381502 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -4,6 +4,14 @@ config BOARD_GOOGLE_CORSOLA_COMMON def_bool n +config BOARD_GOOGLE_KINGLER_COMMON + def_bool n + select BOARD_GOOGLE_CORSOLA_COMMON + +config BOARD_GOOGLE_KRABBY_COMMON + def_bool n + select BOARD_GOOGLE_CORSOLA_COMMON + if BOARD_GOOGLE_CORSOLA_COMMON config VBOOT diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index baeb67a..0953220 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -4,10 +4,14 @@ bool "-> Corsola" select BOARD_GOOGLE_CORSOLA_COMMON +comment "Kingler" + config BOARD_GOOGLE_KINGLER bool "-> Kingler" - select BOARD_GOOGLE_CORSOLA_COMMON + select BOARD_GOOGLE_KINGLER_COMMON + +comment "Krabby" config BOARD_GOOGLE_KRABBY bool "-> Krabby" - select BOARD_GOOGLE_CORSOLA_COMMON + select BOARD_GOOGLE_KRABBY_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/60395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If775532c1a262f3e8b3f11b24cae555844f2bfec Gerrit-Change-Number: 60395 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Move some definations of devapc to common folder
by Rex-BC Chen (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60394 ) Change subject: soc/mediatek/mt8195: Move some definations of devapc to common folder ...................................................................... soc/mediatek/mt8195: Move some definations of devapc to common folder Move some definations of devapc for sharing between MT8195 and MT8186. BUG=b:202871018 TEST=emerge-cherry coreboot; emerge-corsola coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia1769ede790f106a320ead9be7e2a596fe96930a --- A src/soc/mediatek/common/include/soc/devapc_common.h M src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/devapc.h 4 files changed, 52 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/60394/1 diff --git a/src/soc/mediatek/common/include/soc/devapc_common.h b/src/soc/mediatek/common/include/soc/devapc_common.h new file mode 100644 index 0000000..666fc70 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/devapc_common.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_DEVAPC_H +#define SOC_MEDIATEK_COMMON_DEVAPC_H + +#define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, + +#define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) + +#define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, \ + PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, \ + PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) + +#define FORBIDDEN2 FORBIDDEN, FORBIDDEN +#define FORBIDDEN3 FORBIDDEN2, FORBIDDEN +#define FORBIDDEN4 FORBIDDEN3, FORBIDDEN +#define FORBIDDEN5 FORBIDDEN4, FORBIDDEN +#define FORBIDDEN6 FORBIDDEN5, FORBIDDEN +#define FORBIDDEN7 FORBIDDEN6, FORBIDDEN +#define FORBIDDEN10 FORBIDDEN3, FORBIDDEN7 +#define FORBIDDEN11 FORBIDDEN10, FORBIDDEN +#define FORBIDDEN12 FORBIDDEN11, FORBIDDEN +#define FORBIDDEN13 FORBIDDEN12, FORBIDDEN +#define FORBIDDEN14 FORBIDDEN13, FORBIDDEN +#define FORBIDDEN15 FORBIDDEN14, FORBIDDEN + +#define NO_PROTECTION2 NO_PROTECTION, NO_PROTECTION +#define NO_PROTECTION3 NO_PROTECTION2, NO_PROTECTION +#define NO_PROTECTION4 NO_PROTECTION3, NO_PROTECTION + +#endif diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c index 3e86289..3a49e38 100644 --- a/src/soc/mediatek/mt8195/apusys_devapc.c +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <soc/apusys_devapc.h> #include <soc/devapc.h> +#include <soc/devapc_common.h> static const enum domain_id domain_map[] = { DOMAIN_0, DOMAIN_1, DOMAIN_2, DOMAIN_3, DOMAIN_4, DOMAIN_5, DOMAIN_6, DOMAIN_7, diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index 1b0de8c..ac3e6db 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <soc/devapc.h> +#include <soc/devapc_common.h> #include <soc/apusys_devapc.h> static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { diff --git a/src/soc/mediatek/mt8195/include/soc/devapc.h b/src/soc/mediatek/mt8195/include/soc/devapc.h index 5267b3b..a355fdf 100644 --- a/src/soc/mediatek/mt8195/include/soc/devapc.h +++ b/src/soc/mediatek/mt8195/include/soc/devapc.h @@ -76,51 +76,6 @@ unsigned char d_permission[4]; }; -#define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3) \ - (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ - (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, - -#define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) \ - DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3) \ - DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) - -#define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ - PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ - PERM_ATTR14, PERM_ATTR15) \ - DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, \ - PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) \ - DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ - PERM_ATTR10, PERM_ATTR11, \ - PERM_ATTR12, PERM_ATTR13, \ - PERM_ATTR14, PERM_ATTR15) - -#define NO_PROTECTION2 NO_PROTECTION, NO_PROTECTION -#define NO_PROTECTION3 NO_PROTECTION2, NO_PROTECTION - -#define FORBIDDEN2 FORBIDDEN, FORBIDDEN -#define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN -#define FORBIDDEN7 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN -#define FORBIDDEN10 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN -#define FORBIDDEN11 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN -#define FORBIDDEN12 FORBIDDEN11, FORBIDDEN -#define FORBIDDEN13 FORBIDDEN12, FORBIDDEN -#define FORBIDDEN14 FORBIDDEN13, FORBIDDEN -#define FORBIDDEN15 FORBIDDEN14, FORBIDDEN - enum devapc_sys_dom_num { DOM_NUM_INFRA_AO_SYS0 = 16, DOM_NUM_INFRA_AO_SYS1 = 4, -- To view, visit https://review.coreboot.org/c/coreboot/+/60394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1769ede790f106a320ead9be7e2a596fe96930a Gerrit-Change-Number: 60394 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021