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Change subject: mb/google/brya/var/brask: Change TPM I2C to I2C1
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60439/comment/a039abc8_e859bc3a
PS1, Line 114: i2c3
> Should be i2c1 ?
Yes, we need to change this.
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Hello build bot (Jenkins), Tim Wawrzynczak, Alan Huang,
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Change subject: mb/google/brya/var/brask: Change TPM I2C to I2C1
......................................................................
mb/google/brya/var/brask: Change TPM I2C to I2C1
The latest schematics changes the TPM I2C from I2C3 to I2C1.
This patch moves the TPM I2C setting from the board layer to the
baseboard and fixes the TPM I2C bus assignment.
BUG=b:211886429
TEST=build pass
Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c
Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/brask/overridetree.cb
4 files changed, 17 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/60439/2
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60443 )
Change subject: soc/intel/alderlake: Fix incorrect comment about debug consent
......................................................................
soc/intel/alderlake: Fix incorrect comment about debug consent
This patch makes the debug consent for ADL comment default value
comment proper. Default `Platform Debug Consent` value is
2: Enabled (Al probes and tracehub.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ic5eeb4f02d051dc1efba2deaecb51cbc7eac51f5
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/60443/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 335a4f9..280da2a 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -307,7 +307,7 @@
config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
int "Debug Consent for ADL"
- # USB DBC is more common for developers so make this default to 3 if
+ # USB DBC is more common for developers so make this default to 2 if
# SOC_INTEL_DEBUG_CONSENT=y
default 2 if SOC_INTEL_DEBUG_CONSENT
default 0
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Change subject: mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
......................................................................
mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
Due to the CL was merged: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/….
Update to matched id for audio work normal.
1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2.
BUG=b:210542422
TEST=emerge-guybrush coreboot chromeos-bootimage; Download image 14425 and tested audio function.
Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com>
Change-Id: I542f886fe63205777837d7146169177b043cc5f2
---
M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
1 file changed, 1 insertion(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/60442/4
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
......................................................................
mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
Due to the CL was merged: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/….
Update to matched id for audio work normal.
1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2.
BUG=b:210542422
TEST=emerge-guybrush coreboot chromeos-bootimage; Download image 14425 and tested audio function.
Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com>
Change-Id: I542f886fe63205777837d7146169177b043cc5f2
---
M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
1 file changed, 1 insertion(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/60442/3
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Kenneth Chan has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/60442 )
Change subject: mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
......................................................................
mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
Due to the CL was merged: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/….
1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2
Update to matched id for audio work normal.
BUG=b:210542422
TEST=emerge-guybrush coreboot chromeos-bootimage; Download image 14425 and tested audio function.
Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com>
Change-Id: I542f886fe63205777837d7146169177b043cc5f2
---
M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
1 file changed, 1 insertion(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/60442/2
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Change subject: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting
......................................................................
mb/google/guybrush/var/dewatt: disable unused PCIe clock setting
GPP_CLK1 is used for SD and GPP_CLK2 is for WWAN on guybrush.
Disable unused PCIe GPP_CLK1 and GPP_CLK2 for dewatt.
BUG=b:211566312
TEST=emerge-guybrush coreboot
Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com>
Change-Id: If449453bc60ed41e104346429babc06a73acef64
---
M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/60328/4
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60441 )
Change subject: soc/intel/alderlake: Add option to make MRC log silent
......................................................................
soc/intel/alderlake: Add option to make MRC log silent
Typically, FSP-M aka MRC debug log level is default set to `3`
meaning prints all `Load, Error, Warnings & Info` Messages.
Sometime it's too much information to parse even when users
aren't required to have such detailed information hence,
added option to make the MRC serial debug message
silent when user selects `SILENT_FSP_M_DEBUG_MESSAGE` config.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `3`. While user selects `SILENT_FSP_M_DEBUG_MESSAGE`
config `SerialDebugMrcLevel` UPD value is overridden to '0'
aka disable.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
---
M src/drivers/intel/fsp2_0/Kconfig.debug_blob
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
3 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60441/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig.debug_blob b/src/drivers/intel/fsp2_0/Kconfig.debug_blob
index e9e6053..9c814dd 100644
--- a/src/drivers/intel/fsp2_0/Kconfig.debug_blob
+++ b/src/drivers/intel/fsp2_0/Kconfig.debug_blob
@@ -62,4 +62,12 @@
requires platform support to snapshot and verify that config
matches snapshot.
+config SILENT_FSP_M_DEBUG_MESSAGE
+ bool
+ default n
+ help
+ Select this option for silent or quite FSP-M boot even with debug
+ enable FSP-M binary. This feature is helpful to reduce the boot time
+ latency with debug FSP binaries.
+
endif # PLATFORM_USES_FSP2_0
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 5419783..335a4f9 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -320,6 +320,21 @@
0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power),
7:Manual
+config SOC_INTEL_ALDERLAKE_MRC_DEBUG_CONSENT
+ int "Debug Consent for FSP-M"
+ # MRC Serial Debug Message Level `Load, Error, Warnings & Info`
+ # is useful for developers so set the default to `3`.
+ # If SILENT_FSP_M_DEBUG_MESSAGE=y then make FSP-M silent/disable.
+ default 0 if SILENT_FSP_M_DEBUG_MESSAGE
+ default 3
+ help
+ This is to control MRC serial debug interface for FSP-M.
+
+ Desired MRC serial debug level are
+ 0:Disable, 1:Error Only, 2:Error & Warnings,
+ 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event,
+ 5:Load, Error, Warnings, Info & Verbose.
+
config DATA_BUS_WIDTH
int
default 128
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 8959bf7..be266d9 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -312,6 +312,9 @@
static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config)
{
+ /* Set MRC debug level */
+ m_cfg->SerialDebugMrcLevel = CONFIG_SOC_INTEL_ALDERLAKE_MRC_DEBUG_CONSENT;
+
/* Set debug probe type */
m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
--
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