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Change in coreboot[master]: mb/google/corsola: Initialize kingler display
by Hung-Te Lin (Code Review) 29 Dec '21

29 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60398 ) Change subject: mb/google/corsola: Initialize kingler display ...................................................................... mb/google/corsola: Initialize kingler display ANX7625 is used on Kingler board as the eDP bridge IC. Enable ANX7625 and configure display in mainboard_init() to support display in firmware screen. BUG=b:209930699 TEST=saw firmware display on eDP panel of kingler board. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60398 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Makefile.inc A src/mainboard/google/corsola/display.c A src/mainboard/google/corsola/display.h M src/mainboard/google/corsola/gpio.h M src/mainboard/google/corsola/mainboard.c 6 files changed, 145 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index e381502..702c3fc 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -35,6 +35,9 @@ select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_ANALOGIX_ANX7625 config MAINBOARD_DIR string diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index e1e363c..30ee6c1 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -16,6 +16,7 @@ ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-y += chromeos.c +ramstage-y += display.c ramstage-y += mainboard.c ramstage-y += regulator.c ramstage-y += reset.c diff --git a/src/mainboard/google/corsola/display.c b/src/mainboard/google/corsola/display.c new file mode 100644 index 0000000..6e4cbe5 --- /dev/null +++ b/src/mainboard/google/corsola/display.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio_common.h> +#include <soc/i2c.h> +#include <soc/mtcmos.h> + +#include "display.h" +#include "gpio.h" + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_backlight_and_bridge(void) +{ + /* Disable backlight before turning on bridge */ + gpio_output(GPIO_AP_EDP_BKLTEN, 0); + gpio_output(GPIO_BL_PWM_1V8, 0); + gpio_output(GPIO_EN_PP3300_DISP_X, 1); + + /* Turn on bridge */ + gpio_output(GPIO_EDPBRDG_RST_L, 0); + gpio_output(GPIO_EN_PP1000_EDPBRDG, 1); + gpio_output(GPIO_EN_PP1800_EDPBRDG, 1); + gpio_output(GPIO_EN_PP3300_EDPBRDG, 1); + mdelay(14); + gpio_output(GPIO_EDPBRDG_PWREN, 1); + mdelay(10); + gpio_output(GPIO_EDPBRDG_RST_L, 1); +} + +static int anx7625_setup(u8 i2c_bus, struct edid *edid) +{ + if (anx7625_init(i2c_bus) < 0) { + printk(BIOS_ERR, "%s: Can't init ANX7625 bridge\n", __func__); + return -1; + } + if (anx7625_dp_get_edid(i2c_bus, edid) < 0) { + printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); + return -1; + } + return 0; +} + +static int bridge_setup(u8 i2c_bus, struct edid *edid) +{ + if (CONFIG(BOARD_GOOGLE_KINGLER_COMMON)) + return anx7625_setup(i2c_bus, edid); + else + printk(BIOS_ERR, "%s: There is no bridge IC supported\n", __func__); + + return -1; +} + +static int bridge_post_poweron(u8 i2c_bus, struct edid *edid) +{ + if (CONFIG(BOARD_GOOGLE_KINGLER_COMMON)) + return anx7625_dp_start(i2c_bus, edid); + + return 0; +} + +int configure_display(void) +{ + struct edid edid; + const u8 i2c_bus = I2C0; + + printk(BIOS_INFO, "%s: Starting display init\n", __func__); + + configure_backlight_and_bridge(); + mtk_i2c_bus_init(i2c_bus, I2C_SPEED_FAST); + + if (bridge_setup(i2c_bus, &edid) < 0) { + printk(BIOS_ERR, "%s: Failed to set bridge\n", __func__); + return -1; + } + + const char *name = edid.ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, + edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, + edid.mode.refresh); + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + mtk_ddp_init(); + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET); + + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); + return -1; + } + + if (bridge_post_poweron(i2c_bus, &edid) < 0) { + printk(BIOS_ERR, "%s: Failed to post poweron bridge\n", __func__); + return -1; + } + + mtk_ddp_mode_set(&edid); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); + + return 0; +} diff --git a/src/mainboard/google/corsola/display.h b/src/mainboard/google/corsola/display.h new file mode 100644 index 0000000..525422b --- /dev/null +++ b/src/mainboard/google/corsola/display.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ + +int configure_display(void); + +#endif diff --git a/src/mainboard/google/corsola/gpio.h b/src/mainboard/google/corsola/gpio.h index c2f789e..8f8fb72 100644 --- a/src/mainboard/google/corsola/gpio.h +++ b/src/mainboard/google/corsola/gpio.h @@ -9,7 +9,6 @@ #define GPIO_BT_WAKE_AP_ODL GPIO(EINT6) #define GPIO_WIFI_INT_ODL GPIO(EINT7) #define GPIO_DPBRDG_INT_ODL GPIO(EINT8) -#define GPIO_EDPBRDG_INT_ODL GPIO(EINT9) #define GPIO_EC_AP_HPD_OD GPIO(EINT10) #define GPIO_TCHPAD_INT_ODL GPIO(EINT11) #define GPIO_TCHSCR_INT_1V8_ODL GPIO(EINT12) @@ -27,6 +26,17 @@ #define GPIO_EN_SPK GPIO(PERIPHERAL_EN3) #define GPIO_BEEP_ON GPIO(PERIPHERAL_EN4) +/* GPIOs for display */ +#define GPIO_AP_EDP_BKLTEN GPIO(PERIPHERAL_EN5) +#define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) +#define GPIO_EN_PP3300_DISP_X GPIO(PERIPHERAL_EN6) +#define GPIO_EDPBRDG_RST_L GPIO(LCM_RST) +#define GPIO_EN_PP1000_EDPBRDG GPIO(ANT_SEL0) +#define GPIO_EN_PP1800_EDPBRDG GPIO(ANT_SEL1) +#define GPIO_EN_PP3300_EDPBRDG GPIO(ANT_SEL2) +#define GPIO_EDPBRDG_INT_ODL GPIO(EINT9) +#define GPIO_EDPBRDG_PWREN GPIO(DSI_TE) + void setup_chromeos_gpios(void); #endif diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index fa4aa18..910d8d6 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bl31.h> +#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/msdc.h> #include <soc/spm.h> #include <soc/usb.h> +#include "display.h" #include "gpio.h" #include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> @@ -37,6 +39,13 @@ printk(BIOS_ERR, "spm init failed, system suspend may not work\n"); register_reset_to_bl31(); + + if (display_init_required()) { + if (configure_display() < 0) + printk(BIOS_ERR, "%s: Failed to init display\n", __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display init\n", __func__); + } } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/60398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91 Gerrit-Change-Number: 60398 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add DSI driver
by Hung-Te Lin (Code Review) 29 Dec '21

29 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60397 ) Change subject: soc/mediatek/mt8186: Add DSI driver ...................................................................... soc/mediatek/mt8186: Add DSI driver Enable DSI for display. BUG=b:209930699 TEST=Firmware display looked good Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60397 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/include/soc/dsi.h 2 files changed, 61 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index dd7541f..f99bd47 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c +ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8186/include/soc/dsi.h b/src/soc/mediatek/mt8186/include/soc/dsi.h new file mode 100644 index 0000000..2cb9159 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dsi.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 6.9 + */ + +#ifndef SOC_MEDIATEK_MT8186_DSI_H +#define SOC_MEDIATEK_MT8186_DSI_H + +#include <soc/dsi_common.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16 Gerrit-Change-Number: 60397 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add DDP driver
by Hung-Te Lin (Code Review) 29 Dec '21

29 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60396 ) Change subject: soc/mediatek/mt8186: Add DDP driver ...................................................................... soc/mediatek/mt8186: Add DDP driver Add DDP (display controller) driver that supports main path to eDP panel. The output goes to display interface DSI. BUG=b:209930699 TEST=saw firmware display Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60396 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/ddp.c M src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/ddp.h 4 files changed, 436 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index c940d37..dd7541f 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -44,6 +44,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += ../common/auxadc.c +ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c new file mode 100644 index 0000000..6706ed7 --- /dev/null +++ b/src/soc/mediatek/mt8186/ddp.c @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 6.9 + */ + +#include <console/console.h> +#include <edid.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +static void disp_config_main_path_connection(void) +{ + /* + * Main path: + * OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0->DITHER->DSI0 + */ + SET32_BITFIELDS(&mmsys_cfg->disp_ovl0_mout_en, + DISP_OVL0_MOUT_EN, DISP_OVL0_MOUT_TO_RDMA0); + SET32_BITFIELDS(&mmsys_cfg->disp_rdma0_sel_in, + DISP_RDMA0_SEL_IN, DISP_RDMA0_FROM_OVL0); + SET32_BITFIELDS(&mmsys_cfg->mmsys_ovl_con, + DISP_MMSYS_OVL0_CON, DISP_OVL0_GO_BLEND); + SET32_BITFIELDS(&mmsys_cfg->disp_rdma0_sout_sel, + DISP_RDMA0_SOUT_SEL, DISP_RDMA0_SOUT_TO_COLOR0); + SET32_BITFIELDS(&mmsys_cfg->disp_dither0_mout_en, + DISP_DITHER0_MOUT_EN, DISP_DITHER0_MOUT_TO_DSI0); + SET32_BITFIELDS(&mmsys_cfg->disp_dsi0_sel_in, + DISP_DSI0_SEL_IN, DISP_DSI0_FROM_DITHER0); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_layer_smi_id_en(u32 idx) +{ + SET32_BITFIELDS(&disp_ovl[idx]->datapath_con, + SMI_ID_EN, SMI_ID_EN_VAL); +} + +static void ccorr_config(u32 width, u32 height) +{ + struct disp_ccorr_regs *const regs = disp_ccorr; + + write32(&regs->size, width << 16 | height); + + /* Disable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, 0); + SET32_BITFIELDS(&regs->cfg, PQ_CFG_ENGINE_EN, PQ_ENGINE_EN); + + write32(&regs->en, PQ_EN); +} + +static void aal_config(u32 width, u32 height) +{ + struct disp_aal_regs *const regs = disp_aal; + + write32(&regs->size, width << 16 | height); + write32(&regs->output_size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + SET32_BITFIELDS(&regs->cfg, PQ_CFG_ENGINE_EN, 0); + + write32(&regs->en, PQ_EN); +} + +static void gamma_config(u32 width, u32 height) +{ + struct disp_gamma_regs *const regs = disp_gamma; + + write32(&regs->size, width << 16 | height); + + /* Disable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, 0); + + write32(&regs->en, PQ_EN); +} + +static void postmask_config(u32 width, u32 height) +{ + struct disp_postmask_regs *const regs = disp_postmask; + + write32(&regs->size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void dither_config(u32 width, u32 height) +{ + struct disp_dither_regs *const regs = disp_dither; + + write32(&regs->size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(&regs->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 pixel_clk = width * height * vrefresh; + + /* One ovl in main path */ + ovl_set_roi(0, width, height, 0xff0000ff); + ovl_layer_smi_id_en(0); + rdma_config(width, height, pixel_clk, 5 * KiB); + color_start(width, height); + ccorr_config(width, height); + aal_config(width, height); + gamma_config(width, height); + postmask_config(width, height); + dither_config(width, height); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + + /* Turn off M4U port */ + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + printk(BIOS_INFO, "%s: display resolution: %ux%u@%u bpp %u\n", + __func__, width, height, vrefresh, bpp); + + if (!vrefresh) { + vrefresh = 60; + printk(BIOS_INFO, "%s: invalid vrefresh; setting to %u\n", + __func__, vrefresh); + } + + main_disp_path_setup(width, height, vrefresh); + rdma_start(); + ovl_layer_config(fmt, bpp, width, height); +} diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index adb1d59..c90e0cd 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -75,8 +75,19 @@ EFUSEC_BASE = IO_PHYS + 0x01CB0000, MIPITX_BASE = IO_PHYS + 0x01CC0000, MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_MUTEX_BASE = IO_PHYS + 0x04001000, SMI_BASE = IO_PHYS + 0x04002000, SMI_LARB0 = IO_PHYS + 0x04003000, + DISP_OVL0_BASE = IO_PHYS + 0x04005000, + DISP_OVL1_BASE = IO_PHYS + 0x04006000, + DISP_RDMA0_BASE = IO_PHYS + 0x04007000, + DISP_COLOR0_BASE = IO_PHYS + 0x04009000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400B000, + DISP_AAL0_BASE = IO_PHYS + 0x0400C000, + DISP_GAMMA0_BASE = IO_PHYS + 0x0400D000, + DISP_POSTMASK0_BASE = IO_PHYS + 0x0400E000, + DISP_DITHER0_BASE = IO_PHYS + 0x0400F000, DSI0_BASE = IO_PHYS + 0x04013000, }; #endif diff --git a/src/soc/mediatek/mt8186/include/soc/ddp.h b/src/soc/mediatek/mt8186/include/soc/ddp.h new file mode 100644 index 0000000..e66563d --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/ddp.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 6.9 + */ + +#ifndef SOC_MEDIATEK_MT8186_DDP_H +#define SOC_MEDIATEK_MT8186_DDP_H + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/ddp_common.h> +#include <types.h> + +#define SMI_LARB_PORT_L0_OVL_RDMA0 0x388 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10c; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11c[33]; /* 0x11C */ + u32 mmsys_cg_con2; /* 0x1A0 */ + u32 mmsys_cg_set2; /* 0x1A4 */ + u32 mmsys_cg_clr2; /* 0x1A8 */ + u32 reserved_0x1ac[853]; /* 0x1AC */ + u32 reserved_0xf00; /* 0xF00 */ + u32 mmsys_ovl_con; /* 0xF04 */ + u32 reserved_0xf08; /* 0xF08 */ + u32 disp_rdma0_sout_sel; /* 0xF0C */ + u32 reserved_0xf10; /* 0xF10 */ + u32 disp_ovl0_2l_mout_en; /* 0xF14 */ + u32 disp_ovl0_mout_en; /* 0xF18 */ + u32 reserved_0xf1c; /* 0xF1C */ + u32 disp_dither0_mout_en; /* 0xF20 */ + u32 reserved_0xf24; /* 0xF24 */ + u32 disp_rdma0_sel_in; /* 0xF28 */ + u32 reserved_0xf2c; /* 0xF2C */ + u32 disp_dsi0_sel_in; /* 0xF30 */ + u32 reserved_0xf34[2]; /* 0xF34 */ + u32 disp_rdma1_mout_en; /* 0xF3C */ + u32 disp_rdma1_sel_in; /* 0xF40 */ + u32 disp_dpi0_sel_in; /* 0xF44 */ +}; +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); +check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0); +check_member(mmsys_cfg_regs, mmsys_ovl_con, 0xF04); +check_member(mmsys_cfg_regs, disp_rdma0_sout_sel, 0xF0C); +check_member(mmsys_cfg_regs, disp_ovl0_mout_en, 0xF18); +check_member(mmsys_cfg_regs, disp_dither0_mout_en, 0xF20); +check_member(mmsys_cfg_regs, disp_rdma0_sel_in, 0xF28); +check_member(mmsys_cfg_regs, disp_dsi0_sel_in, 0xF30); + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[16]; +}; + +struct disp_ccorr_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[27]; + u32 shadow; +}; +check_member(disp_ccorr_regs, shadow, 0xA0); + +struct disp_gamma_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_gamma_regs, size, 0x30); + +struct disp_aal_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[47]; + u32 shadow; + u32 reserved3[249]; + u32 output_size; +}; +check_member(disp_aal_regs, shadow, 0xF0); +check_member(disp_aal_regs, output_size, 0x4D8); + +struct disp_postmask_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 reserved0[4]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_postmask_regs, size, 0x30); + +struct disp_dither_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[51]; + u32 disp_dither_0; +}; +check_member(disp_dither_regs, disp_dither_0, 0x100); + +/* + * DISP_REG_CONFIG_MMSYS_CG_CON0 + * Configures free-run clock gating 0 + * 0: Enable clock + * 1: Clock gating + */ +enum { + CG_CON0_DISP_MUTEX0 = BIT(0), + CG_CON0_APB_MM_BUS = BIT(1), + CG_CON0_DISP_OVL0 = BIT(2), + CG_CON0_DISP_RDMA0 = BIT(3), + CG_CON0_DISP_OVL0_2L = BIT(4), + CG_CON0_DISP_WDMA0 = BIT(5), + CG_CON0_DISP_RSZ0 = BIT(7), + CG_CON0_DISP_AAL0 = BIT(8), + CG_CON0_DISP_CCORR0 = BIT(9), + CG_CON0_DISP_COLOR0 = BIT(10), + CG_CON0_SMI_INFRA = BIT(11), + CG_CON0_DISP_GAMMA0 = BIT(13), + CG_CON0_DISP_POSTMASK0 = BIT(14), + CG_CON0_DISP_DITHER0 = BIT(16), + CG_CON0_SMI_COMMON = BIT(17), + CG_CON0_DISP_DSI0 = BIT(19), + CG_CON0_DISP_FAKE_ENG0 = BIT(20), + CG_CON0_DISP_FAKE_ENG1 = BIT(21), + CG_CON0_SMI_GALS = BIT(22), + CG_CON0_SMI_IOMMU = BIT(24), + CG_CON0_DISP_ALL = CG_CON0_DISP_MUTEX0 | + CG_CON0_APB_MM_BUS | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_SMI_INFRA | + CG_CON0_DISP_GAMMA0 | + CG_CON0_DISP_POSTMASK0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_SMI_COMMON | + CG_CON0_DISP_DSI0 | + CG_CON0_SMI_GALS | + CG_CON0_SMI_IOMMU, + CG_CON0_ALL = 0xFFFFFFFF, +}; + +enum { + CG_CON2_DSI0_DSI_CK_DOMAIN = BIT(0), + CG_CON2_DISP_26M = BIT(10), + CG_CON2_DISP_ALL = CG_CON2_DSI0_DSI_CK_DOMAIN | + CG_CON2_DISP_26M, + CG_CON2_ALL = 0xFFFFFFFF, +}; + +DEFINE_BITFIELD(DISP_OVL0_MOUT_EN, 3, 0) +DEFINE_BITFIELD(DISP_RDMA0_SEL_IN, 3, 0) +DEFINE_BITFIELD(DISP_MMSYS_OVL0_CON, 1, 0) +DEFINE_BITFIELD(DISP_RDMA0_SOUT_SEL, 3, 0) +DEFINE_BITFIELD(DISP_DITHER0_MOUT_EN, 3, 0) +DEFINE_BITFIELD(DISP_DSI0_SEL_IN, 3, 0) + +DEFINE_BIT(SMI_ID_EN, 0) +DEFINE_BIT(PQ_CFG_RELAY_MODE, 0) +DEFINE_BIT(PQ_CFG_ENGINE_EN, 1) + +#define DISP_OVL0_MOUT_TO_RDMA0 BIT(0) +#define DISP_RDMA0_FROM_OVL0 0 +#define DISP_OVL0_GO_BLEND BIT(0) +#define DISP_RDMA0_SOUT_TO_COLOR0 1 +#define DISP_DITHER0_MOUT_TO_DSI0 BIT(0) +#define DISP_DSI0_FROM_DITHER0 1 + +#define SMI_ID_EN_VAL BIT(0) + +enum { + MUTEX_MOD_DISP_OVL0 = BIT(0), + MUTEX_MOD_DISP_RDMA0 = BIT(2), + MUTEX_MOD_DISP_COLOR0 = BIT(4), + MUTEX_MOD_DISP_CCORR0 = BIT(5), + MUTEX_MOD_DISP_AAL0 = BIT(7), + MUTEX_MOD_DISP_GAMMA0 = BIT(8), + MUTEX_MOD_DISP_POSTMASK0 = BIT(9), + MUTEX_MOD_DISP_DITHER0 = BIT(10), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | + MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | + MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_POSTMASK0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +#define PQ_EN BIT(0) +#define PQ_RELAY_MODE BIT(0) +#define PQ_ENGINE_EN BIT(1) + +static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_BASE; +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; +static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; +static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; +static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; +static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; +static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1 Gerrit-Change-Number: 60396 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: Add board common config for kingler and krabby
by Hung-Te Lin (Code Review) 29 Dec '21

29 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60395 ) Change subject: mb/google/corsola: Add board common config for kingler and krabby ...................................................................... mb/google/corsola: Add board common config for kingler and krabby Add common configs to help implementing board-specific logic (for example using different eDP bridge IC drivers). BUG=b:209930699 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If775532c1a262f3e8b3f11b24cae555844f2bfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60395 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 14 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 193cafd..e381502 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -4,6 +4,14 @@ config BOARD_GOOGLE_CORSOLA_COMMON def_bool n +config BOARD_GOOGLE_KINGLER_COMMON + def_bool n + select BOARD_GOOGLE_CORSOLA_COMMON + +config BOARD_GOOGLE_KRABBY_COMMON + def_bool n + select BOARD_GOOGLE_CORSOLA_COMMON + if BOARD_GOOGLE_CORSOLA_COMMON config VBOOT diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index baeb67a..0953220 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -4,10 +4,14 @@ bool "-> Corsola" select BOARD_GOOGLE_CORSOLA_COMMON +comment "Kingler" + config BOARD_GOOGLE_KINGLER bool "-> Kingler" - select BOARD_GOOGLE_CORSOLA_COMMON + select BOARD_GOOGLE_KINGLER_COMMON + +comment "Krabby" config BOARD_GOOGLE_KRABBY bool "-> Krabby" - select BOARD_GOOGLE_CORSOLA_COMMON + select BOARD_GOOGLE_KRABBY_COMMON 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If775532c1a262f3e8b3f11b24cae555844f2bfec Gerrit-Change-Number: 60395 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: Fully calibrate DRAM
by Hung-Te Lin (Code Review) 29 Dec '21

29 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60386 ) Change subject: mb/google/corsola: Fully calibrate DRAM ...................................................................... mb/google/corsola: Fully calibrate DRAM Initialize and calibrate DRAM in romstage. DRAM full calibration logs: dram_init: dram init end (result: 1) DRAM-K: Full calibration passed in 20014 msecs TEST=DRAM full calibration pass. BUG=b:202871018 Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I80a18a8be5b1d47a5f0f7afed9601c0884e69035 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60386 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Makefile.inc M src/mainboard/google/corsola/romstage.c A src/mainboard/google/corsola/sdram_configs.c 3 files changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index 1a9a1c28..e1e363c 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -11,6 +11,7 @@ romstage-y += chromeos.c romstage-y += regulator.c romstage-y += romstage.c +romstage-y += sdram_configs.c ramstage-y += memlayout.ld ramstage-y += boardid.c diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c index aff496b..8d03b5b 100644 --- a/src/mainboard/google/corsola/romstage.c +++ b/src/mainboard/google/corsola/romstage.c @@ -3,6 +3,7 @@ #include <arch/stages.h> #include <console/console.h> #include <delay.h> +#include <soc/emi.h> #include <soc/mt6366.h> #include <soc/pll_common.h> #include <soc/regulator.h> @@ -26,4 +27,5 @@ mt6366_init(); raise_little_cpu_freq(); rtc_boot(); + mtk_dram_init(); } diff --git a/src/mainboard/google/corsola/sdram_configs.c b/src/mainboard/google/corsola/sdram_configs.c new file mode 100644 index 0000000..f565f53 --- /dev/null +++ b/src/mainboard/google/corsola/sdram_configs.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +const struct sdram_info *get_sdram_config(void) +{ + /* + * The MT8186 platform supports "dram adaptive" feature to + * automatically detect dram information, including channel, rank, die size..., + * and can automatically configure EMI settings. + * So we will be passing a placeholder param blob. + */ + static struct sdram_info params; + return &params; +} 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80a18a8be5b1d47a5f0f7afed9601c0884e69035 Gerrit-Change-Number: 60386 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Fix include guard naming for emi.h
by Yu-Ping Wu (Code Review) 29 Dec '21

29 Dec '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60440 ) Change subject: soc/mediatek: Fix include guard naming for emi.h ...................................................................... soc/mediatek: Fix include guard naming for emi.h Fix the name of the include guard for soc/mediatek/common/include/soc/emi.h. BUG=none TEST=emerge-corsola coreboot BRANCH=none Change-Id: Iddac3467959545b7db141545aaa2a135536f44f1 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/common/include/soc/emi.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/60440/1 diff --git a/src/soc/mediatek/common/include/soc/emi.h b/src/soc/mediatek/common/include/soc/emi.h index 994d35a..60206d8 100644 --- a/src/soc/mediatek/common/include/soc/emi.h +++ b/src/soc/mediatek/common/include/soc/emi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_EMI_H -#define SOC_MEDIATEK_EMI_H +#ifndef SOC_MEDIATEK_COMMON_EMI_H +#define SOC_MEDIATEK_COMMON_EMI_H #include <soc/dramc_param.h> @@ -16,4 +16,4 @@ u32 get_ddr_type(void); void init_dram_by_params(struct dramc_param *dparam); -#endif /* SOC_MEDIATEK_MT8192_EMI_H */ +#endif /* SOC_MEDIATEK_COMMON_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddac3467959545b7db141545aaa2a135536f44f1 Gerrit-Change-Number: 60440 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brask: Change TPM I2C to I2C1
by David Wu (Code Review) 29 Dec '21

29 Dec '21

Attention is currently required from: Tim Wawrzynczak, Zhuohao Lee. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60439 ) Change subject: mb/google/brya/var/brask: Change TPM I2C to I2C1 ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60439/comment/5c1c05f4_079ab860 PS1, Line 114: i2c3 Should be i2c1 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/60439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c Gerrit-Change-Number: 60439 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 29 Dec 2021 07:46:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add DRAM full calibration support
by Hung-Te Lin (Code Review) 29 Dec '21

29 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60318 ) Change subject: soc/mediatek/mt8186: Add DRAM full calibration support ...................................................................... soc/mediatek/mt8186: Add DRAM full calibration support Use common SoC drivers for DRAM calibration support. TEST=build pass. BUG=b:202871018 Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60318 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/mediatek/mt8186/Kconfig M src/soc/mediatek/mt8186/Makefile.inc 2 files changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index 5393baa..11a18f2 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -6,6 +6,7 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select ARM64_USE_ARM_TRUSTED_FIRMWARE + select CACHE_MRC_SETTINGS select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 5d3f668..c940d37 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -26,10 +26,14 @@ romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c +romstage-y += ../common/memory.c +romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -78,6 +82,14 @@ $(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \ ) +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8186_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/60318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7 Gerrit-Change-Number: 60318 Gerrit-PatchSet: 14 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add header files to support DRAM calibration
by Hung-Te Lin (Code Review) 29 Dec '21

29 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60385 ) Change subject: soc/mediatek/mt8186: Add header files to support DRAM calibration ...................................................................... soc/mediatek/mt8186: Add header files to support DRAM calibration Remove emi.h because emi.h is defined in common/include/soc. Add dramc_param.h and dramc_soc.h to prepare for implementation of DRAM full calibration. TEST=build pass. BUG=b:202871018 Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60385 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8186/emi.c A src/soc/mediatek/mt8186/include/soc/dramc_param.h A src/soc/mediatek/mt8186/include/soc/dramc_soc.h D src/soc/mediatek/mt8186/include/soc/emi.h 4 files changed, 208 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c index 169b353..48a7b3e 100644 --- a/src/soc/mediatek/mt8186/emi.c +++ b/src/soc/mediatek/mt8186/emi.c @@ -11,3 +11,8 @@ { return (size_t)4 * GiB; } + +void mt_set_emi(struct dramc_param *dparam) +{ + /* Do nothing */ +} diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_param.h b/src/soc/mediatek/mt8186/include/soc/dramc_param.h new file mode 100644 index 0000000..81f518f --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dramc_param.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ + +/* + * NOTE: This file is shared between coreboot and dram blob. Any change in this + * file should be synced to the other repository. + */ + +#include <stdint.h> +#include <sys/types.h> +#include <soc/dramc_soc.h> + +#define DRAMC_PARAM_HEADER_VERSION 1 + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, + DRAMC_ERR_INIT_DRAM, + DRAMC_ERR_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_FAST_CALIBRATION, +}; + +enum DRAMC_PARAM_FLAGS { + DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, +}; + +enum SDRAM_DVFS_FLAG { + DRAMC_DISABLE_DVFS, + DRAMC_ENABLE_DVFS, +}; + +enum SDRAM_DDR_TYPE { + DDR_TYPE_DISCRETE, + DDR_TYPE_EMCP, +}; + +enum SDRAM_DDR_GEOMETRY_TYPE { + DDR_TYPE_2CH_2RK_4GB_2_2, + DDR_TYPE_2CH_2RK_6GB_3_3, + DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, + DDR_TYPE_2CH_1RK_4GB_4_0, + DDR_TYPE_2CH_2RK_6GB_2_4, + DDR_TYPE_2CH_2RK_8GB_4_4, +}; + +enum SDRAM_VOLTAGE_TYPE { + SDRAM_VOLTAGE_NVCORE_NVDRAM, + SDRAM_VOLTAGE_HVCORE_HVDRAM, + SDRAM_VOLTAGE_LVCORE_LVDRAM, +}; + +struct dramc_param_header { + u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ + u16 size; /* size of whole dramc_param, update in the coreboot */ + u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ + u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ + u16 config; /* DRAMC_PARAM_CONFIG, set in coreboot */ +}; + +struct sdram_info { + u32 ddr_type; /* SDRAM_DDR_TYPE */ + u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ +}; + +struct sdram_params { + u32 rank_num; + u16 num_dlycell_perT; + u16 delay_cell_timex100; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + + /* CBT */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + s8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* Gating */ + u8 gating_MCK[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* TX perbit */ + u8 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit */ + u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* TX OE */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; +}; + +struct emi_mdl { + u32 cona_val; + u32 conh_val; + u32 conf_val; + u32 chn_cona_val; +}; + +struct ddr_base_info { + u32 config_dvfs; /* SDRAM_DVFS_FLAG */ + struct sdram_info sdram; + u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ + u32 support_ranks; + u64 rank_size[RANK_MAX]; + struct emi_mdl emi_config; + DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +const struct sdram_info *get_sdram_config(void); +struct dramc_param *get_dramc_param_from_blob(void *blob); +void dump_param_header(const void *blob); +int initialize_dramc_param(void *blob); + +#endif /* __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h new file mode 100644 index 0000000..34e8414 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ +#define __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ + +typedef enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX, +} DRAM_CHANNEL_T; + +typedef enum { + RANK_0 = 0, + RANK_1, + RANK_MAX, +} DRAM_RANK_T; + +/* DRAM SHUFFLE RG type */ +typedef enum { + DRAM_DFS_SHUFFLE_1 = 0, + DRAM_DFS_SHUFFLE_2, + DRAM_DFS_SHUFFLE_3, + DRAM_DFS_SHUFFLE_4, + DRAM_DFS_SHUFFLE_5, + DRAM_DFS_SHUFFLE_6, + DRAM_DFS_SHUFFLE_7, + DRAM_DFS_SHUFFLE_8, + DRAM_DFS_SHUFFLE_9, + DRAM_DFS_SHUFFLE_10, + DRAM_DFS_SHUFFLE_MAX, +} DRAM_DFS_SHUFFLE_TYPE_T; + +/* + * Internal CBT mode enum + * 1. Calibration flow uses vGet_Dram_CBT_Mode to + * differentiate between mixed vs non-mixed LP4 + * 2. Declared as dram_cbt_mode[RANK_MAX] internally to + * store each rank's CBT mode type + */ +typedef enum { + CBT_NORMAL_MODE = 0, + CBT_BYTE_MODE1, +} DRAM_CBT_MODE_T; + +#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX + +#define DQS_NUMBER_LP4 2 +#define DQS_BIT_NUMBER 8 +#define DQ_DATA_WIDTH_LP4 16 + +#endif /* __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/emi.h b/src/soc/mediatek/mt8186/include/soc/emi.h deleted file mode 100644 index decfa07..0000000 --- a/src/soc/mediatek/mt8186/include/soc/emi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is created based on MT8186 Functional Specification - * Chapter number: 4.8 - */ - -#ifndef SOC_MEDIATEK_MT8186_EMI_H -#define SOC_MEDIATEK_MT8186_EMI_H - -#include <stddef.h> - -size_t sdram_size(void); - -#endif /* SOC_MEDIATEK_MT8186_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387 Gerrit-Change-Number: 60385 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
by Casper Chang (Code Review) 29 Dec '21

29 Dec '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Meera Ravindranath. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60417 ) Change subject: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Hi Casper, […] Hi Meera, As we're preparing the SW bundle to upcoming Primus DVT build, we may need this change to verify the process of the DVT pilot which including suspend stress test. If ES CPU will not be used in the future, we'd like to use this CL as work around to make suspend stress worked for Primus EVT unit first. Please share the platform level patch when it's available. We'll follow up and verify it on Primus EVT units. Thank you very much. -- To view, visit https://review.coreboot.org/c/coreboot/+/60417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac Gerrit-Change-Number: 60417 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Wed, 29 Dec 2021 07:42:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021