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Change subject: ChromeOS: Create pseudo-device ACPI NVS
......................................................................
Patch Set 10:
(1 comment)
File src/vendorcode/google/chromeos/gnvs.c:
https://review.coreboot.org/c/coreboot/+/55502/comment/d7e57b9b_a04f7016
PS10, Line 115: .acpi_inject_dsdt = chromeos_dsdt_generator,
> It turns out there is really no need for the device node after all and we could call chromeos_dsdt_g […]
Good eye... I wonder if we could just stick this into the acpi_fill_ssdt (would have to check if there is any reason it can't be in SSDT). But also you are right, a device node is not really required... you could just add
```
if (CONFIG(CHROMEOS))
chromeos_dsdt_generator();
```
in place of the acpi_inject_dsdt call() in acpi.c if the xeon DSDT injector can be removed too.
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Change subject: ChromeOS: Drop spurious <vc/google/chromeos/chromeos.h>
......................................................................
Patch Set 8: Code-Review+2
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Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
Patch Set 3:
(1 comment)
File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/49fb797e_3e556e51
PS3, Line 47: depends on TPM2 && RESUME_PATH_SAME_AS_BOOT
RESUME_PATH_SAME_AS_BOOT depends on HAVE_ACPI_RESUME (aka S3). Guybrush does not support S3, so HAVE_ACPI_RESUME and RESUME_PATH_SAME_AS_BOOT are not selected. Since RESUME_PATH_SAME_AS_BOOT is checked in disable_platform_hierarchy, I don't think the depends is required here.
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Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Note: This needs to be multiple CLs. I will split it up after initial feedback.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
soc/amd/psp_verstage: Init TPM on S0i3 resume
Add option to initialize the TPM in PSP verstage during s0i3 resume.
This is needed if the TPM is reset in s0i3. FSDL is handling
restoring everything else, so only the minimum TPM initialization is done.
BUG=b:200578885
TEST=Multiple cycles of S0i3 suspend resume. ~50ms of additional delay.
BRANCH=None
Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/verstage.c
M src/security/vboot/vboot_common.h
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/common/psp_verstage/fch.c
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
M src/vendorcode/google/chromeos/Kconfig
9 files changed, 109 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/3
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Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132335):
https://review.coreboot.org/c/coreboot/+/58870/comment/7cb8879e_3b4e2edd
PS2, Line 274: if(retval) {
space required before the open parenthesis '('
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
soc/amd/psp_verstage: Init TPM on S0i3 resume
Add option to initialize the TPM in PSP verstage during s0i3 resume.
This is needed if the TPM is reset in s0i3. The PSP is handling
restoring everything else, so only the minimum TPM initialize is done.
BUG=b:200578885
TEST=Multiple cycles of S0i3 suspend resume
BRANCH=None
Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/verstage.c
M src/security/vboot/vboot_common.h
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/common/psp_verstage/fch.c
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
M src/vendorcode/google/chromeos/Kconfig
9 files changed, 110 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/2
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I'd like you to reexamine a change. Please visit
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Change subject: ChromeOS: Drop spurious <vc/google/chromeos/chromeos.h>
......................................................................
ChromeOS: Drop spurious <vc/google/chromeos/chromeos.h>
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/drivers/intel/fsp1_1/romstage.c
M src/ec/google/chromeec/vboot_storage.c
M src/mainboard/google/auron/ec.c
M src/mainboard/google/brya/variants/anahera/gpio.c
M src/mainboard/google/brya/variants/brask/gpio.c
M src/mainboard/google/brya/variants/felwinter/gpio.c
M src/mainboard/google/brya/variants/gimble/gpio.c
M src/mainboard/google/brya/variants/kano/gpio.c
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/redrix/gpio.c
M src/mainboard/google/brya/variants/taeko/gpio.c
M src/mainboard/google/cyan/ec.c
M src/mainboard/google/dedede/variants/blipper/gpio.c
M src/mainboard/google/dedede/variants/boten/gpio.c
M src/mainboard/google/dedede/variants/gooey/gpio.c
M src/mainboard/google/dedede/variants/metaknight/gpio.c
M src/mainboard/google/foster/mainboard.c
M src/mainboard/google/gru/mainboard.c
M src/mainboard/google/nyan/mainboard.c
M src/mainboard/google/nyan_big/mainboard.c
M src/mainboard/google/nyan_blaze/mainboard.c
M src/mainboard/google/oak/mainboard.c
M src/mainboard/google/veyron/mainboard.c
M src/mainboard/google/veyron/romstage.c
M src/mainboard/google/veyron_mickey/mainboard.c
M src/mainboard/google/veyron_mickey/romstage.c
M src/mainboard/google/veyron_rialto/mainboard.c
M src/mainboard/google/veyron_rialto/romstage.c
M src/mainboard/intel/strago/ec.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/cr50_enable_update.c
M src/vendorcode/google/chromeos/vpd_calibration.c
33 files changed, 4 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/58923/8
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