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Change subject: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_mch()`
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> That being said, I agree that this change in behavior should be accounted for in the commit message. […]
maybe "Use the `popcnt()` helper instead of looping over the first CONFIG_MAX_CPUS bits and counting the bits set and use unsigned types." ?
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Change subject: soc/intel: move SGX ACPI code to block/acpi
......................................................................
Patch Set 2:
(1 comment)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/58925/comment/a664c1ba_2d260c70
PS2, Line 1239: void sgx_fill_ssdt(void);
> > Why is this function declaration in common code, and not somewhere in soc/intel? […]
I personally don't see the need to move the code out of soc/intel/common/block/sgx, but I won't oppose. Just don't leave this declaration here 😜
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Change subject: soc/intel: generate SSDT instead of using GNVS for SGX
......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/common/block/sgx/sgx.c:
https://review.coreboot.org/c/coreboot/+/58394/comment/bc88c835_b86c3ab1
PS6, Line 245: /* Get EPC base and size.
: * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or
: * Higher for enumeration of SGX Resources. Same Table mentions
: * about return values of the CPUID */
Would be good to update this comment to match our coding style
https://review.coreboot.org/c/coreboot/+/58394/comment/84619b8e_303aabe7
PS6, Line 261:
nit: drop blank line?
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Change subject: src/lib: Add FW_CONFIG_SOURCE_VPD
......................................................................
Patch Set 10:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58839/comment/1f50f3fe_182321d4
PS9, Line 7: CONIFG_
> CONFIG
Ack
File src/lib/fw_config.c:
https://review.coreboot.org/c/coreboot/+/58839/comment/ea8e031a_5e613805
PS9, Line 49: int32_t
> nit: I would prefer this type to match the type of `vpd_get_int`, which just takes an `int *`
Ack
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Change subject: soc/amd/*/include/smi: fix off-by-one in SCIMAPS defines
......................................................................
Patch Set 1: Code-Review+2
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Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58860 )
Change subject: Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUE
......................................................................
Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUE
This reduces the number of selects required in the SOC_SPECIFIC_OPTIONS.
BUG=b:179699789
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I7f1364fc269ea5ec17982bf750a164a3290adb0e
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---
M src/Kconfig
M src/soc/amd/cezanne/Kconfig
2 files changed, 4 insertions(+), 5 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/Kconfig b/src/Kconfig
index e4ddf0c..89849ec 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -677,12 +677,12 @@
config COOP_MULTITASKING
def_bool n
- depends on TIMER_QUEUE && ARCH_X86 && CPU_INFO_V2
+ select TIMER_QUEUE
+ depends on ARCH_X86 && CPU_INFO_V2
help
Cooperative multitasking allows callbacks to be multiplexed on the
- main thread of ramstage. With this enabled it allows for multiple
- execution paths to take place when they have udelay() calls within
- their code.
+ main thread. With this enabled it allows for multiple execution paths
+ to take place when they have udelay() calls within their code.
config NUM_THREADS
int
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 65bf2bf..f36f912 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -73,7 +73,6 @@
select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI
select SSE2
- select TIMER_QUEUE
select UDK_2017_BINDING
select X86_AMD_FIXED_MTRRS
select X86_AMD_INIT_SIPI
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Change subject: Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUE
......................................................................
Patch Set 3: Code-Review+2
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