coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the top
by Raul Rangel (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58953 ) Change subject: soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the top ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79 Gerrit-Change-Number: 58953 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Nov 2021 16:18:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS()
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Karthik Ramasubramanian. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58899 ) Change subject: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS() ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > It is boilerplate, but it's also only a few lines, and this means generating a function with a macro […] I do not like the function part of this either, let me find another way. -- To view, visit https://review.coreboot.org/c/coreboot/+/58899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Gerrit-Change-Number: 58899 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 16:17:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Create pseudo-device ACPI NVS
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 ) Change subject: ChromeOS: Create pseudo-device ACPI NVS ...................................................................... Patch Set 10: (2 comments) Patchset: PS5: > ChromeOS NVS is already separated from GNVS. […] Ack File src/vendorcode/google/chromeos/gnvs.c: https://review.coreboot.org/c/coreboot/+/55502/comment/51426150_01339d5f PS10, Line 115: .acpi_inject_dsdt = chromeos_dsdt_generator, It turns out there is really no need for the device node after all and we could call chromeos_dsdt_generator directly. Also this and some intel/xeon are the only users of .acpi_inject_dsdt so there might be chance to discuss if we really need this. -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Nov 2021 16:11:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: google/guybrush: Move SPI speed override
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Karthik Ramasubramanian, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58945 ) Change subject: google/guybrush: Move SPI speed override ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > moving the spi speed override out of chromeos.c sounds good to me. […] Actually I think I will want to keep the guard indeed. Happy with the new filename? -- To view, visit https://review.coreboot.org/c/coreboot/+/58945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Gerrit-Change-Number: 58945 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Nov 2021 16:07:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Michael Niewöhner (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 47: Code-Review-2 (1 comment) Patchset: PS46: > Wow. […] Lean, can you provide more info on what is required to open-source the Zephyr code? You say it's Apache-licensed, so I assume a customer of you could open-source it by themselves? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 47 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Nov 2021 16:06:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: move SGX ACPI code to block/acpi
by Michael Niewöhner (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58925 ) Change subject: soc/intel: move SGX ACPI code to block/acpi ...................................................................... Patch Set 2: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/58925/comment/8d768a9f_8235f49a PS2, Line 1239: void sgx_fill_ssdt(void); > Why is this function declaration in common code, and not somewhere in soc/intel? ugh, that wasn't intended... should have been in `soc/intel/common/block/include/intelblocks/acpi.h` > Why move it? intelblocks/sgx.h looks like the right place? bc it's ACPI; other declarations are there, too -- To view, visit https://review.coreboot.org/c/coreboot/+/58925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I089d0ee97c37df2be060b5996183201bfa9b49ca Gerrit-Change-Number: 58925 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Nov 2021 16:04:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Lee Leahy, Tim Wawrzynczak, Julius Werner, Huang Jin, Patrick Rudolph. Hello build bot (Jenkins), Lee Leahy, Tim Wawrzynczak, Huang Jin, Julius Werner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58923 to look at the new patch set (#6). Change subject: [test] fix indirect-include ...................................................................... [test] fix indirect-include Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp1_1/romstage.c M src/ec/google/chromeec/vboot_storage.c M src/mainboard/google/auron/ec.c M src/mainboard/google/brya/variants/anahera/gpio.c M src/mainboard/google/brya/variants/brask/gpio.c M src/mainboard/google/brya/variants/felwinter/gpio.c M src/mainboard/google/brya/variants/gimble/gpio.c M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/taeko/gpio.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/dedede/variants/blipper/gpio.c M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/gooey/gpio.c M src/mainboard/google/dedede/variants/metaknight/gpio.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/gru/mainboard.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/intel/strago/ec.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/vpd_calibration.c 32 files changed, 3 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/58923/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/nvidia,qualcomm: Fix indirect includes
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58949 to look at the new patch set (#2). Change subject: soc/nvidia,qualcomm: Fix indirect includes ...................................................................... soc/nvidia,qualcomm: Fix indirect includes Avoid indirect <vc/google/chromeos/chromeos.h> as the files really only need <security/vboot/vboot_common.h>. Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/gale/verstage.c M src/soc/nvidia/tegra124/verstage.c D src/soc/nvidia/tegra210/include/soc/verstage.h D src/soc/qualcomm/ipq40xx/include/soc/verstage.h 4 files changed, 2 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/58949/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94 Gerrit-Change-Number: 58949 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the top
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58953 ) Change subject: soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the top ...................................................................... soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the top Since all other defines for the number of certain things are at the top of the file, move NUMBER_SMITYPES there as well to keep things consistent. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79 --- M src/soc/amd/cezanne/include/soc/smi.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/smi.h 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/58953/1 diff --git a/src/soc/amd/cezanne/include/soc/smi.h b/src/soc/amd/cezanne/include/soc/smi.h index f0948bb..aad4123 100644 --- a/src/soc/amd/cezanne/include/soc/smi.h +++ b/src/soc/amd/cezanne/include/soc/smi.h @@ -8,6 +8,7 @@ #define SMI_GEVENTS 24 #define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 +#define NUMBER_SMITYPES 160 #define SMI_EVENT_STATUS 0x0 #define SMI_EVENT_ENABLE 0x04 @@ -138,7 +139,7 @@ /* 153-155 Reserved */ #define SMITYPE_CFGTRAP0 156 /* 157-159 Reserved */ -#define NUMBER_SMITYPES 160 + #define TYPE_TO_MASK(X) (1 << (X) % 32) #define SMI_REG_SMISTS0 0x80 diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 8256b21..dba3bea 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -8,6 +8,7 @@ #define SMI_GEVENTS 24 #define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 +#define NUMBER_SMITYPES 160 #define SMI_EVENT_STATUS 0x0 #define SMI_EVENT_ENABLE 0x04 @@ -140,7 +141,7 @@ /* 153-155 Reserved */ #define SMITYPE_CFGTRAP0 156 /* 157-159 Reserved */ -#define NUMBER_SMITYPES 160 + #define TYPE_TO_MASK(X) (1 << (X) % 32) #define SMI_REG_SMISTS0 0x80 diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 0e0bc37..3ce41df 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -6,6 +6,7 @@ #define SMI_GEVENTS 24 #define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 +#define NUMBER_SMITYPES 160 #define SMI_EVENT_STATUS 0x0 #define SMI_EVENT_ENABLE 0x04 @@ -138,7 +139,7 @@ /* 153-155 Reserved */ #define SMITYPE_CFGTRAP0 156 /* 157-159 Reserved */ -#define NUMBER_SMITYPES 160 + #define TYPE_TO_MASK(X) (1 << (X) % 32) #define SMI_REG_SMISTS0 0x80 -- To view, visit https://review.coreboot.org/c/coreboot/+/58953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79 Gerrit-Change-Number: 58953 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/include/smi: fix off-by-one in SCIMAPS defines
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58952 ) Change subject: soc/amd/*/include/smi: fix off-by-one in SCIMAPS defines ...................................................................... soc/amd/*/include/smi: fix off-by-one in SCIMAPS defines SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap returns early when the scimap is greater or equal than SCIMAPS, so for SMITYPE_ACDC_TIMER it returned early without doing what was expected from it to do despite that being a valid value, so fix this off-by-one. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb --- M src/soc/amd/cezanne/include/soc/smi.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/smi.h 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/58952/1 diff --git a/src/soc/amd/cezanne/include/soc/smi.h b/src/soc/amd/cezanne/include/soc/smi.h index dc299a5..f0948bb 100644 --- a/src/soc/amd/cezanne/include/soc/smi.h +++ b/src/soc/amd/cezanne/include/soc/smi.h @@ -6,7 +6,7 @@ #include <types.h> #define SMI_GEVENTS 24 -#define SCIMAPS 58 +#define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 #define SMI_EVENT_STATUS 0x0 diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index e86809e..8256b21 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -6,7 +6,7 @@ #include <types.h> #define SMI_GEVENTS 24 -#define SCIMAPS 58 +#define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 #define SMI_EVENT_STATUS 0x0 diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 6162475..0e0bc37 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -4,7 +4,7 @@ #define AMD_STONEYRIDGE_SMI_H #define SMI_GEVENTS 24 -#define SCIMAPS 58 +#define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 #define SMI_EVENT_STATUS 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/58952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb Gerrit-Change-Number: 58952 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021