coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Nico Huber (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 50: (2 comments) Patchset: PS50: https://review.coreboot.org/c/flashrom/+/58883 File src/soc/intel/elkhartlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/e2f1be42_b864ed5a PS49, Line 127: m_cfg->PchPseEnable = CONFIG(PSE_ENABLE); > We will see if there is something useable here and add a follow-up. […] I don't know what OK means on your scale. You outrank me anyway, so there is no point in asking me for permission and it's not a technical matter anyway. From a social point of view, no, it's not OK. Upstream coreboot is mostly maintained by individuals of the community in their spare time, same for developer support. We have worked hard to make things around blobs maintainable and to avoid error-prone code that might not boot and results in support requests. It becomes more tedious if we have to repeat every tiny discussion for every tiny blob added. Ignoring the hard work naturally looks like you don't care about the feelings of the people committed to coreboot. Also, pushing patches like this prematurely forward makes it much harder to get authors like Sheng accepted by the hard working folks. Not only now but also long-term. If somebody will look at the Git history in a year or so, they don't see this discussion, they see the code and who wrote it. And with every TODO comment you add, you gamble. If it isn't handled before somebody stumbles over it, it will make things look even worse. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 50 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 16:00:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/psp_verstage: Get vb2_context early
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59017 ) Change subject: soc/amd/psp_verstage: Get vb2_context early ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/psp_verstage/psp_verstage.c: https://review.coreboot.org/c/coreboot/+/59017/comment/e2479098_b07c3dd9 PS1, Line 226: verstage_soc_early_init Did you actually see verstage_soc_early_init fail? Or did you just noticed the error in the code? -- To view, visit https://review.coreboot.org/c/coreboot/+/59017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Gerrit-Change-Number: 59017 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:58:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Remove global chip_config variable
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Patrick Rudolph, Tim Chu. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58605 ) Change subject: soc/intel/xeon_sp: Remove global chip_config variable ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/skx/cpu.c: https://review.coreboot.org/c/coreboot/+/58605/comment/69215d93_fb894d95 PS1, Line 48: cpu->chip_info; Can we move the config and use config_of_soc instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/58605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaffdf9716ca5265c4575f92b3b3151d3bf7e45dd Gerrit-Change-Number: 58605 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:51:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/haswell: Remove the fake lapic
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Tristan Corrick, Angel Pons, Alexander Couzens, Patrick Rudolph. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58604 ) Change subject: cpu/intel/haswell: Remove the fake lapic ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/haswell/acpi.c: https://review.coreboot.org/c/coreboot/+/58604/comment/fb46922c_b052ffd0 PS1, Line 175: s0ix_enable Why is this config on the CPU? It sounds like using config_of_soc() would be a better place for this config data. -- To view, visit https://review.coreboot.org/c/coreboot/+/58604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69f9c1fe71a773e1fba0942d8a785b6ad26dd9a0 Gerrit-Change-Number: 58604 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:50:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]cpu/x86/mp_init.c: Copy BSP chip_info to AP devices
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58603 ) Change subject: [RFC]cpu/x86/mp_init.c: Copy BSP chip_info to AP devices ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58603/comment/4e771bd7_7e93ae4f PS1, Line 9: few : workarounds like storing the BSP chip_info in a global variable or : using a fake lapic device would become obsolete > Can you point me to some examples? AH, just need to look at the rest of the patch train ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/58603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9b83b096da07821b7c1f9b36b3e311cd751718 Gerrit-Change-Number: 58603 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:46:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]cpu/x86/mp_init.c: Copy BSP chip_info to AP devices
by Raul Rangel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58603 ) Change subject: [RFC]cpu/x86/mp_init.c: Copy BSP chip_info to AP devices ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58603/comment/09ecf417_22b66aff PS1, Line 9: few : workarounds like storing the BSP chip_info in a global variable or : using a fake lapic device would become obsolete Can you point me to some examples? Patchset: PS1: > Sorry, tried to review this, but the cpu_info() function starts with a […] Yeah, I think you are right. I just didn't trust it. It felt like a brittle hack to me so I didn't want to touch it. IMO, it should be using __builtin_frame_address(0). All MP_INIT boards are using CPU_INFO_V2 now. File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/58603/comment/c44dc5e4_ed717e66 PS1, Line 392: new->chip_info = info->cpu->chip_info; Is it possible for `new->chip_info` to be already set if it was defined in the device tree? -- To view, visit https://review.coreboot.org/c/coreboot/+/58603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9b83b096da07821b7c1f9b36b3e311cd751718 Gerrit-Change-Number: 58603 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:46:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 50: (13 comments) Patchset: PS46: > > > @Nico I wonder how you want to integrate that minimal sample exactly. […] Yes, this UPD has already been set to 0 if PSE is disabled. /* PSE (Intel Programmable Services Engine) switch */ m_cfg->PchPseEnable = CONFIG(PSE_ENABLE); File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/55367/comment/1f617253_7869a3df PS49, Line 203: be > *to* be? Done https://review.coreboot.org/c/coreboot/+/55367/comment/8f5e1a69_6adc62f0 PS49, Line 202: that is designed as an Asymmetric : Multi-Processing (AMP) system > AIUI, Intel describes the whole SoC as AMP. Some cores are in the CPU complex and […] Yes Nico you are right :) Done reworked. https://review.coreboot.org/c/coreboot/+/55367/comment/b863b2fa_7e41ca30 PS49, Line 204: added to CBFS and loaded by FSP to run PSE. > > Maybe a misunderstanding. We don't explicitly mention that a ramstage binary […] Done reworded. File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/cbdb438e_6952e160 PS49, Line 52: CONFIG_PSE_IMAGE > Did you mean CONFIG_PSE_ENABLE? Done https://review.coreboot.org/c/coreboot/+/55367/comment/c0b71471_1ee05877 PS49, Line 66: > Well it's not the common coreboot practice. This is not the […] Valid concern here thanks. Added ADD_PSE_IMAGE_TO_CBFS config to guard the FW file. File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/d2fe9768_68feb560 PS49, Line 383: /* PSE devices config */ > I don't understand this comment. Done reworked. https://review.coreboot.org/c/coreboot/+/55367/comment/136a6b79_8990302f PS49, Line 384: /* PSE DMA */ > That's literally what the indentifier says, such a comment is just distraction. Done removed all of them. https://review.coreboot.org/c/coreboot/+/55367/comment/5836ac3c_42697ae1 PS49, Line 423: > Nit, missing line break after the /* Done https://review.coreboot.org/c/coreboot/+/55367/comment/ff89601c_5b2ffb32 PS49, Line 426: * as it still allows user to change these params from devicetree. > Yes, this could be written more precise her. […] Done reworked the wordings. https://review.coreboot.org/c/coreboot/+/55367/comment/1796a6e0_a4f8113d PS49, Line 436: 0x0 > Why is this hex? Done https://review.coreboot.org/c/coreboot/+/55367/comment/013db742_edf5a34b PS49, Line 438: 0x3 > Why is this hex? Done https://review.coreboot.org/c/coreboot/+/55367/comment/b9497f0f_e8a293f5 PS49, Line 438: // > Please use common comment style. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 50 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:40:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by build bot (Jenkins) (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Patrick Rudolph, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 50: (8 comments) File src/soc/intel/elkhartlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132588): https://review.coreboot.org/c/coreboot/+/55367/comment/aed6f249_a207b15e PS50, Line 386: FSP_ARRAY_LOAD(params->PchPseDmaSbInterruptEnable, config->PseDmaSbIntEn); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132588): https://review.coreboot.org/c/coreboot/+/55367/comment/b21d22bf_257cc54a PS50, Line 388: FSP_ARRAY_LOAD(params->PchPseUartSbInterruptEnable, config->PseUartSbIntEn); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132588): https://review.coreboot.org/c/coreboot/+/55367/comment/140814ed_83586221 PS50, Line 391: FSP_ARRAY_LOAD(params->PchPseQepSbInterruptEnable, config->PseQepSbIntEn); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132588): https://review.coreboot.org/c/coreboot/+/55367/comment/6d361a33_f5ee5935 PS50, Line 393: FSP_ARRAY_LOAD(params->PchPseI2cSbInterruptEnable, config->PseI2cSbIntEn); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132588): https://review.coreboot.org/c/coreboot/+/55367/comment/b59f46b5_d3aaffd2 PS50, Line 395: FSP_ARRAY_LOAD(params->PchPseI2sSbInterruptEnable, config->PseI2sSbIntEn); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132588): https://review.coreboot.org/c/coreboot/+/55367/comment/6c2e7293_4c01e5d8 PS50, Line 397: FSP_ARRAY_LOAD(params->PchPseSpiSbInterruptEnable, config->PseSpiSbIntEn); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132588): https://review.coreboot.org/c/coreboot/+/55367/comment/7c0c1f93_6104d5b9 PS50, Line 401: FSP_ARRAY_LOAD(params->PchPseCanSbInterruptEnable, config->PseCanSbIntEn); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132588): https://review.coreboot.org/c/coreboot/+/55367/comment/247c0d17_498ab6cf PS50, Line 428: else { else should follow close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 50 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:36:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Werner Zeh (Code Review) 08 Nov '21

08 Nov '21

1 0

Change in coreboot[master]: [WIP] mb/google,intel: Split chromeos.c files
by build bot (Jenkins) (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59018 ) Change subject: [WIP] mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 1: (1 comment) File src/mainboard/intel/kblrvp/bootmode.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132586): https://review.coreboot.org/c/coreboot/+/59018/comment/eef083ae_ec4c1949 PS1, Line 21: if (google_chromeec_get_switches() & suspect code indent for conditional statements (16, 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/59018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ccd31edc5ab6c4bc7890a8de1ae270141d18a7 Gerrit-Change-Number: 59018 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 15:29:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021