coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/picasso/include/southbridge: drop unused aoac_devs struct
by Paul Fagerburg (Code Review) 08 Nov '21

08 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58972 ) Change subject: soc/amd/picasso/include/southbridge: drop unused aoac_devs struct ...................................................................... soc/amd/picasso/include/southbridge: drop unused aoac_devs struct Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ida8d767a5b56bdf59747362ddf68372436573895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58972 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 0 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 2cc1c62..f547f86 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -128,22 +128,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -typedef struct aoac_devs { - unsigned int :7; - unsigned int ic2e:1; /* 7: I2C2 */ - unsigned int ic3e:1; /* 8: I2C3 */ - unsigned int ic4e:1; /* 9: I2C4 */ - unsigned int :1; - unsigned int ut0e:1; /* 11: UART0 */ - unsigned int ut1e:1; /* 12: UART1 */ - unsigned int :3; - unsigned int ut2e:1; /* 16: UART2 */ - unsigned int :9; - unsigned int ut3e:1; /* 26: UART3 */ - unsigned int espi:1; /* 27: ESPI */ - unsigned int :4; -} __packed aoac_devs_t; - void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/58972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida8d767a5b56bdf59747362ddf68372436573895 Gerrit-Change-Number: 58972 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/lib: Add FW_CONFIG_SOURCE_VPD
by Paul Fagerburg (Code Review) 08 Nov '21

08 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58839 ) Change subject: src/lib: Add FW_CONFIG_SOURCE_VPD ...................................................................... src/lib: Add FW_CONFIG_SOURCE_VPD Read fw_config value from VPD. This new option can be used where chrome EC is not supported like pre-silicon platform and fw_config can be updated by VPD tool in OS. TEST= boot to OS and read fw_config from vpd 1. Boot to OS 2. Write "fw_config" in VPD ex) vpd -i "RW_VPD" -s "fw_config"="1" 3. reboot and check fw_config value from coreboot log Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58839 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/Kconfig M src/lib/fw_config.c 2 files changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index e30152d..e1d0c00 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -416,6 +416,16 @@ local image to preempt the mainboard selected source and can be used as FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option. +config FW_CONFIG_SOURCE_VPD + bool "Obtain Firmware Configuration value from VPD" + depends on FW_CONFIG && VPD + default n + help + With this option enabled coreboot will look for the 32bit firmware + configuration value in VPD key name "fw_config". This option will + override other sources and allow the local image to preempt the mainboard + selected source and can be used for other FW_CONFIG_SOURCEs fallback option. + config HAVE_RAMPAYLOAD bool diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index 3546736..72cf225 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -11,6 +11,7 @@ #include <lib.h> #include <stdbool.h> #include <stdint.h> +#include <drivers/vpd/vpd.h> uint64_t fw_config_get(void) { @@ -44,6 +45,17 @@ fw_config_value); } + if (CONFIG(FW_CONFIG_SOURCE_VPD) && fw_config_value == UNDEFINED_FW_CONFIG) { + int vpd_value; + if (vpd_get_int("fw_config", VPD_RW_THEN_RO, &vpd_value)) { + fw_config_value = vpd_value; + printk(BIOS_INFO, "FW_CONFIG value from VPD is 0x%" PRIx64 "\n", + fw_config_value); + } else + printk(BIOS_WARNING, "%s: Could not get fw_config from vpd\n", + __func__); + } + return fw_config_value; } 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 Gerrit-Change-Number: 58839 Gerrit-PatchSet: 13 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/lib/fw_config: Change fw_config sources priority
by Paul Fagerburg (Code Review) 08 Nov '21

08 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58833 ) Change subject: src/lib/fw_config: Change fw_config sources priority ...................................................................... src/lib/fw_config: Change fw_config sources priority Request fw_config values from various sources (as enabled via Kconfig) until a valid value has been read. With this change, Chrome EC CBI takes precedence over CBFS fw_config. TEST=select both configs and check fallback behavior. 1. select both FW_CONFIG_SOURCE_CHROMEEC_CBI and FW_CONFIG_SOURCE_CBFS 2. check log for reading fw_config from CBI and CBFS Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58833 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/Kconfig M src/lib/fw_config.c 2 files changed, 29 insertions(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 89849ec..e30152d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -395,16 +395,6 @@ Enable support for probing devices with fw_config. This is a simple bitmask broken into fields and options for probing. -config FW_CONFIG_SOURCE_CBFS - bool "Obtain Firmware Configuration value from CBFS" - depends on FW_CONFIG - default n - help - With this option enabled coreboot will look for the 32bit firmware - configuration value in CBFS at the selected prefix with the file name - "fw_config". This option will override other sources and allow the - local image to preempt the mainboard selected source. - config FW_CONFIG_SOURCE_CHROMEEC_CBI bool "Obtain Firmware Configuration value from Google Chrome EC CBI" depends on FW_CONFIG && EC_GOOGLE_CHROMEEC @@ -415,6 +405,17 @@ is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was found in CBFS. +config FW_CONFIG_SOURCE_CBFS + bool "Obtain Firmware Configuration value from CBFS" + depends on FW_CONFIG + default n + help + With this option enabled coreboot will look for the 32bit firmware + configuration value in CBFS at the selected prefix with the file name + "fw_config". This option will override other sources and allow the + local image to preempt the mainboard selected source and can be used as + FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option. + config HAVE_RAMPAYLOAD bool diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index 8e45c00..3546736 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -21,30 +21,29 @@ if (fw_config_value_initialized) return fw_config_value; fw_config_value_initialized = true; - - /* Look in CBFS to allow override of value. */ - if (CONFIG(FW_CONFIG_SOURCE_CBFS)) { - if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value, - sizeof(fw_config_value)) != sizeof(fw_config_value)) { - printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n", - __func__); - fw_config_value = UNDEFINED_FW_CONFIG; - } else { - printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", - fw_config_value); - return fw_config_value; - } - } + fw_config_value = UNDEFINED_FW_CONFIG; /* Read the value from EC CBI. */ if (CONFIG(FW_CONFIG_SOURCE_CHROMEEC_CBI)) { - if (google_chromeec_cbi_get_fw_config(&fw_config_value)) { - printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__); - fw_config_value = UNDEFINED_FW_CONFIG; - } + if (google_chromeec_cbi_get_fw_config(&fw_config_value)) + printk(BIOS_WARNING, "%s: Could not get fw_config from CBI\n", + __func__); + else + printk(BIOS_INFO, "FW_CONFIG value from CBI is 0x%" PRIx64 "\n", + fw_config_value); } - printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value); + /* Look in CBFS to allow override of value. */ + if (CONFIG(FW_CONFIG_SOURCE_CBFS) && fw_config_value == UNDEFINED_FW_CONFIG) { + if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value, + sizeof(fw_config_value)) != sizeof(fw_config_value)) + printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n", + __func__); + else + printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", + fw_config_value); + } + return fw_config_value; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Gerrit-Change-Number: 58833 Gerrit-PatchSet: 9 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/elog/elog: Add timestamps to elog_init
by Paul Fagerburg (Code Review) 08 Nov '21

08 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58957 ) Change subject: drivers/elog/elog: Add timestamps to elog_init ...................................................................... drivers/elog/elog: Add timestamps to elog_init elog init requires doing a lot of SPI transactions. This change makes it clear how long we spend initializing elog. BUG=b:179699789 TEST=Boot guybrush and see elog init timestamps 114:started elog init 3,029,116 (88) 115:finished elog init 3,071,281 (42,165) Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58957 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/elog/elog.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 98fe552..de3e1bb 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -56,6 +56,8 @@ TS_DELAY_END = 111, TS_READ_UCODE_START = 112, TS_READ_UCODE_END = 113, + TS_ELOG_INIT_START = 114, + TS_ELOG_INIT_END = 115, /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ TS_START_COPYVER = 501, @@ -200,6 +202,8 @@ { TS_DELAY_END, "Forced delay end" }, { TS_READ_UCODE_START, "started reading uCode" }, { TS_READ_UCODE_END, "finished reading uCode" }, + { TS_ELOG_INIT_START, "started elog init" }, + { TS_ELOG_INIT_END, "finished elog init" }, { TS_START_COPYVER, "starting to load verstage" }, { TS_END_COPYVER, "finished loading verstage" }, diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index ca2ec6e..37df182 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -16,6 +16,7 @@ #include <smbios.h> #include <stdint.h> #include <string.h> +#include <timestamp.h> #define ELOG_MIN_AVAILABLE_ENTRIES 2 /* Shrink when this many can't fit */ #define ELOG_SHRINK_PERCENTAGE 25 /* Percent of total area to remove */ @@ -749,6 +750,9 @@ } elog_state.elog_initialized = ELOG_BROKEN; + if (!ENV_SMM) + timestamp_add_now(TS_ELOG_INIT_START); + elog_debug("%s()\n", __func__); /* Set up the backing store */ @@ -781,6 +785,10 @@ if (ENV_PAYLOAD_LOADER) elog_add_boot_count(); + + if (!ENV_SMM) + timestamp_add_now(TS_ELOG_INIT_END); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f Gerrit-Change-Number: 58957 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Add ASYNC_FILE_LOADING
by Paul Fagerburg (Code Review) 08 Nov '21

08 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58861 ) Change subject: soc/amd/cezanne: Add ASYNC_FILE_LOADING ...................................................................... soc/amd/cezanne: Add ASYNC_FILE_LOADING This gives us a knob that can be controlled via a .config to enable/disable file preloading. I left the option disabled because there is currently a race condition that can cause data corruption when using the SPI DMA controller. The fix will actually introduce a boot time regression because the preloads are happening at the same time as the elog init. I want to keep preloading disabled for now until I get all the sequencing worked out. BUG=b:179699789 TEST=Boot guybrush and verify no preloading happens. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58861 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 11 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index f36f912..a09e9f9 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -19,7 +19,6 @@ select CPU_INFO_V2 select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE - select COOP_MULTITASKING select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -31,7 +30,6 @@ select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select PARALLEL_MP_AP_WORK - select PAYLOAD_PRELOAD select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK @@ -53,7 +51,6 @@ select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC - select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI @@ -194,6 +191,17 @@ Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86. +config ASYNC_FILE_LOADING + bool "Loads files from SPI asynchronously" + select COOP_MULTITASKING + select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + select PAYLOAD_PRELOAD + help + When enabled, the platform will use the LPC SPI DMA controller to + asynchronously load contents from the SPI ROM. This will improve + boot time because the CPUs can be performing useful work while the + SPI contents are being preloaded. + config RAMBASE hex default 0x10000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/58861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 Gerrit-Change-Number: 58861 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: 3rdparty/amd_blobs: advance submodule pointer
by Paul Fagerburg (Code Review) 08 Nov '21

08 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58989 ) Change subject: 3rdparty/amd_blobs: advance submodule pointer ...................................................................... 3rdparty/amd_blobs: advance submodule pointer This adds the following commits from the submodule: * cezanne: Upgrade blobs to 1.0.0.5 * cezanne: Upgrade ABL to ver. 0x19036070 * cezanne: Upgrade SMU FW to 64.52.0 * cezanne: Upgrade SMU to 64.57.0 * cezanne: Update ABLs to 0x1A296070 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id7b3f5d38d34c2714548dff92b7b83fb2628e936 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58989 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 75c8cb5..f638765 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 75c8cb53516eb3e9a65e6b9bd69144e761eb0081 +Subproject commit f638765f17cdca735b69229f4f0479562bcb7526 -- To view, visit https://review.coreboot.org/c/coreboot/+/58989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7b3f5d38d34c2714548dff92b7b83fb2628e936 Gerrit-Change-Number: 58989 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/thread: Switch to using types.h
by Rob Barnes (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58990 ) Change subject: lib/thread: Switch to using types.h ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26b37d3e38852d72fcb6ff07ed578b0879e55dd Gerrit-Change-Number: 58990 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 14:40:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Nico Huber (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (3 comments) File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/8ea7e29f_b91df4af PS49, Line 66: > > Well, no better solution from the top of my head, and I'm not paid […] Well it's not the common coreboot practice. This is not the only case where a blob option exists, should be build tested but no blob is available. Making the file optional and warn if it isn't added is the usual, accepted approach AFAIK. A TODO would be good enough for a neutral (0 score) review from my side. File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/6d5744cd_030a752e PS49, Line 385: FSP_ARRAY_LOAD > > > I do not see exactly how the macro itself hides the types from memcpy(). > > > > It doesn't, I said it hides the implementation (hides that memcpy() is used). > OK, I see. > > > > > From gcc's point of view > > > > I'm more concerned about the reviewers and human readers point of view. > The former version of it was even worse readable for the reviewer. So I guess the macro at least increases readability with the burden that the reader needs to know its implementation. Plus the burden to decide to either accept the bad implementation or ask the author to fix the macro they are using. File src/soc/intel/elkhartlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/c1b44fab_c034541d PS49, Line 127: m_cfg->PchPseEnable = CONFIG(PSE_ENABLE); > Do we have a CBFS API that can check for a file without loading it? I don't know. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 14:26:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
by Marco Chen (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Frank Chu, Zhuohao Lee, Karthik Ramasubramanian. Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/dedede/variants/galtic/variant.c: https://review.coreboot.org/c/coreboot/+/58734/comment/951c4b94_b9f653cb PS6, Line 23: return "wifi_sar-galtic.hex"; If WIFI_SAR_CBFS_DEFAULT_FILENAME is wifi_sar-galtic.hex then we can leave this one to line 32 and comment the default file is wifi_sar-galtic.hex. https://review.coreboot.org/c/coreboot/+/58734/comment/96899391_2bf2181e PS6, Line 32: return "WIFI_SAR_CBFS_DEFAULT_FILENAME"; Where is the CL for new CONFIG_WIFI_SAR_CBFS_FILEPATH? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/58734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Gerrit-Change-Number: 58734 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Marco Chen <marcochen(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 13:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/psp_verstage: Get vb2_context early
by Rob Barnes (Code Review) 08 Nov '21

08 Nov '21

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59017 ) Change subject: soc/amd/psp_verstage: Get vb2_context early ...................................................................... soc/amd/psp_verstage: Get vb2_context early Calling reboot_into_recovery with NULL context fails. Initialize ctx early so it can be used for reboot_into_recovery if an error occurs. BUG=None TEST=Boot guybrush, suspend/resume guybrush BRANCH=None Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/soc/amd/common/psp_verstage/psp_verstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/59017/1 diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 9f27159..91ed7b6 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -220,12 +220,13 @@ svc_write_postcode(POSTCODE_CONSOLE_INIT); console_init(); + ctx = vboot_get_context(); svc_write_postcode(POSTCODE_EARLY_INIT); retval = verstage_soc_early_init(); if (retval) { svc_debug_print("verstage_soc_early_init failed\n"); - reboot_into_recovery(NULL, retval); + reboot_into_recovery(ctx, retval); } svc_debug_print("calling verstage_mainboard_early_init\n"); @@ -240,7 +241,6 @@ vboot_run_logic(); - ctx = vboot_get_context(); retval = check_cmos_recovery(); if (retval) reboot_into_recovery(ctx, retval); -- To view, visit https://review.coreboot.org/c/coreboot/+/59017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Gerrit-Change-Number: 59017 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021