coreboot-gerrit November 2021

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Change in coreboot[master]: google/cyan: Split chromeos.c
by Kyösti Mälkki (Code Review) 08 Nov '21

08 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59015 ) Change subject: google/cyan: Split chromeos.c ...................................................................... google/cyan: Split chromeos.c Change-Id: Iace21fb93658648e90b56a8d90a9b00155976cbb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/cyan/Makefile.inc A src/mainboard/google/cyan/bootmode.c M src/mainboard/google/cyan/chromeos.c A src/mainboard/google/cyan/onboard.h 4 files changed, 21 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/59015/1 diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 4d10b66..b9f858f 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -2,7 +2,6 @@ bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += spd/spd.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/cyan/bootmode.c b/src/mainboard/google/cyan/bootmode.c new file mode 100644 index 0000000..a212d23 --- /dev/null +++ b/src/mainboard/google/cyan/bootmode.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> +#include <soc/gpio.h> +#include "onboard.h" + +int get_write_protect_state(void) +{ + return !!gpio_get(WP_GPIO); +} diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 4123600..5c1cc8b 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -3,12 +3,10 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -/* The WP status pin lives on MF_ISH_GPIO_4 */ -#define WP_GPIO GP_E_22 +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -20,11 +18,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !!gpio_get(WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h new file mode 100644 index 0000000..dd33a38 --- /dev/null +++ b/src/mainboard/google/cyan/onboard.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CYAN_ONBOARD_H +#define CYAN_ONBOARD_H + +/* Write protect active high. */ +#define WP_GPIO GP_E_22 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iace21fb93658648e90b56a8d90a9b00155976cbb Gerrit-Change-Number: 59015 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/cyan: Clean up write_protect_state()
by Kyösti Mälkki (Code Review) 08 Nov '21

08 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59014 ) Change subject: google/cyan: Clean up write_protect_state() ...................................................................... google/cyan: Clean up write_protect_state() The commentary was wrong, write_protect_state() is only called in ramstage at the moment, and only if MRC_SETTINGS_PROTECT is selected. Implementation of get_gpio() eventually does the MMIO read, so BOARD_GOOGLE_CYAN was not a special case. Change-Id: I96ca871110bcf2fc1485bd042ed137d51b822a20 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/cyan/chromeos.c 1 file changed, 1 insertion(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59014/1 diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index c193d18..4123600 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -3,20 +3,13 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/mmio.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> /* The WP status pin lives on MF_ISH_GPIO_4 */ -#define WP_STATUS_PAD_CFG0 0x4838 -#define WP_STATUS_PAD_CFG1 0x483C - #define WP_GPIO GP_E_22 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -29,30 +22,7 @@ int get_write_protect_state(void) { - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. - * Configuring this GPIO as input so that there isn't any ambiguity - * in the reading. - */ -#if ENV_ROMSTAGE - if (CONFIG(BOARD_GOOGLE_CYAN)) { - write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0), - (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); - write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1), - PAD_CONFIG1_DEFAULT0); - } else { - gpio_input_pullup(WP_GPIO); - } -#endif - - /* WP is enabled when the pin is reading high. */ - if (CONFIG(BOARD_GOOGLE_CYAN)) { - return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) - & PAD_VAL_HIGH); - } else { - return !!gpio_get(WP_GPIO); - } + return !!gpio_get(WP_GPIO); } static const struct cros_gpio cros_gpios[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96ca871110bcf2fc1485bd042ed137d51b822a20 Gerrit-Change-Number: 59014 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google,intel: Split chromeos.c files
by Kyösti Mälkki (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59011 to look at the new patch set (#2). Change subject: mb/google,intel: Split chromeos.c files ...................................................................... mb/google,intel: Split chromeos.c files Move all the low-level GPIO support in bootmode.c files and build them for all stages. Keep ChromeOS related ACPI and lbtable support in chromeos.c files and build them only for ramstage. Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/Makefile.inc A src/mainboard/google/auron/bootmode.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/Makefile.inc A src/mainboard/google/beltino/bootmode.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/Makefile.inc A src/mainboard/google/butterfly/bootmode.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/jecht/Makefile.inc A src/mainboard/google/jecht/bootmode.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/link/Makefile.inc A src/mainboard/google/link/bootmode.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/Makefile.inc A src/mainboard/google/parrot/bootmode.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/slippy/Makefile.inc A src/mainboard/google/slippy/bootmode.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/Makefile.inc A src/mainboard/google/stout/bootmode.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/Makefile.inc A src/mainboard/intel/baskingridge/bootmode.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/Makefile.inc A src/mainboard/intel/emeraldlake2/bootmode.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/strago/Makefile.inc A src/mainboard/intel/strago/bootmode.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/samsung/lumpy/Makefile.inc A src/mainboard/samsung/lumpy/bootmode.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/Makefile.inc A src/mainboard/samsung/stumpy/bootmode.c M src/mainboard/samsung/stumpy/chromeos.c 39 files changed, 342 insertions(+), 278 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59011/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Hsuan-ting Chen (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Hsuan Ting Chen, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Andrey Petrov, Yu-Ping Wu, Patrick Rudolph, Felix Held. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58253 ) Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Patch Set 3: (1 comment) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/58253/comment/ac6cdfc7_01d893cd PS2, Line 7: Revert "Revert > Reland […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Gerrit-Change-Number: 58253 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 10:57:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Subrata Banik (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Subrata Banik, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56628 to look at the new patch set (#23). Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... arch/x86: Refactor the SMBIOS type 17 write function List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/smbios.c M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/device/dram/spd.c M src/include/device/dram/spd.h M src/include/dimm_info_util.h M src/include/spd.h M src/lib/dimm_info_util.c M src/mainboard/scaleway/tagada/ramstage.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/soc/amd/common/fsp/dmi.c M src/soc/amd/common/pi/amd_late_init.c M src/soc/intel/common/smbios.c M tests/lib/Makefile.inc M tests/lib/dimm_info_util-test.c 15 files changed, 402 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56628/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 23 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Subrata Banik (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56628 to look at the new patch set (#22). Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... arch/x86: Refactor the SMBIOS type 17 write function List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/smbios.c M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/device/dram/spd.c M src/include/device/dram/spd.h M src/include/dimm_info_util.h M src/include/spd.h M src/lib/dimm_info_util.c M src/mainboard/scaleway/tagada/ramstage.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/soc/amd/common/fsp/dmi.c M src/soc/amd/common/pi/amd_late_init.c M src/soc/intel/common/smbios.c M tests/lib/Makefile.inc M tests/lib/dimm_info_util-test.c 15 files changed, 402 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56628/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 22 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Subrata Banik (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56628 ) Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... Patch Set 21: (4 comments) File src/include/device/dram/spd.h: https://review.coreboot.org/c/coreboot/+/56628/comment/f777ec8b_0cdb5b5f PS21, Line 14: __packed > Sure, and i think changing the order would make more sense rather __packed here Ack File tests/lib/dimm_info_util-test.c: https://review.coreboot.org/c/coreboot/+/56628/comment/1f3b7edb_de933516 PS21, Line 189: const LargestIntegralType udimm_allowed[] = { : DDR5_SPD_UDIMM, DDR5_SPD_MINI_UDIMM, : }; : : const LargestIntegralType rdimm_allowed[] = { DDR5_SPD_RDIMM, DDR5_SPD_MINI_RDIMM }; : > could you merge all of these tests into one, which would get `udimm_allowed`, `rdimm_allowed` and `e […] Ack https://review.coreboot.org/c/coreboot/+/56628/comment/82193848_04898c50 PS21, Line 215: struct memory_info > How about: `struct smbios_form_factor_test_info`? Would it be better? Ack https://review.coreboot.org/c/coreboot/+/56628/comment/797f7cbf_b4a08596 PS21, Line 219: { MEMORY_TYPE_DDR2, test_smbios_form_factor_to_spd_mod_type_on_ddr2 }, : { MEMORY_TYPE_DDR3, test_smbios_form_factor_to_spd_mod_type_on_ddr3 }, : { MEMORY_TYPE_DDR4, test_smbios_form_factor_to_spd_mod_type_on_ddr4 }, : { MEMORY_TYPE_DDR5, test_smbios_form_factor_to_spd_mod_type_on_ddr5 }, > I think, that ddr tests can be in another test case, than lpddrx. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 21 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 09:53:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/tests: Add libcbfs/cbfs_core-test test case
by Yu-Ping Wu (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jakub Czapiga, Paul Fagerburg, Julius Werner, Jan Dabros. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58327 ) Change subject: libpayload/tests: Add libcbfs/cbfs_core-test test case ...................................................................... Patch Set 2: (1 comment) File payloads/libpayload/tests/mocks/cbfs_file_mock.c: https://review.coreboot.org/c/coreboot/+/58327/comment/b0434a5f_d19f9ec3 PS2, Line 5: cbfs_cache [Partial review] What do we need this for? Tests can be run without this. -- To view, visit https://review.coreboot.org/c/coreboot/+/58327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib246a891242f5a514f2f142699800eeb407de4f9 Gerrit-Change-Number: 58327 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 09:32:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add SPI driver support
by Hung-Te Lin (Code Review) 08 Nov '21

08 Nov '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58966 ) Change subject: soc/mediatek/mt8186: Add SPI driver support ...................................................................... soc/mediatek/mt8186: Add SPI driver support Add SPI controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Ruwen Liu <ot_ruwen.liu(a)mediatek.com> Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58966 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/spi.h M src/soc/mediatek/mt8186/spi.c 3 files changed, 140 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index a68d051..cb07ac0 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -6,14 +6,14 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c wdt.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c -verstage-$(CONFIG_SPI_FLASH) += spi.c +verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c wdt.c @@ -22,7 +22,7 @@ romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c wdt.c @@ -30,7 +30,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h index fbf3995..15e7b91 100644 --- a/src/soc/mediatek/mt8186/include/soc/spi.h +++ b/src/soc/mediatek/mt8186/include/soc/spi.h @@ -8,7 +8,22 @@ #ifndef MTK_MT8186_SPI_H #define MTK_MT8186_SPI_H -#include <spi-generic.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 6 + +#define GET_SCK_REG(x) x->spi_cfg2_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) + +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) + +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) enum { SPI_NOR_GPIO_SET0 = 0, diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index 4a1c13c..87f669d 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -7,17 +7,116 @@ #include <assert.h> #include <device/mmio.h> +#include <spi_flash.h> #include <soc/addressmap.h> #include <soc/flash_controller_common.h> #include <soc/gpio.h> #include <soc/spi.h> +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(SPI2_CSB), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(SPI3_CSB), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(EINT11), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(SPI5_CSB), + } +}; + struct pad_func { gpio_t gpio; u8 func; }; #define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} +#define PAD_FUNC_GPIO(name) {GPIO(name), 0} + +static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(SPI0_MI, SPI0_MI_A), + PAD_FUNC_GPIO(SPI0_CSB), + PAD_FUNC(SPI0_MO, SPI0_MO_A), + PAD_FUNC(SPI0_CLK, SPI0_CLK_A), + }, + { + PAD_FUNC(SPI1_MI, SPI1_MI_A), + PAD_FUNC_GPIO(SPI1_CSB), + PAD_FUNC(SPI1_MO, SPI1_MO_A), + PAD_FUNC(SPI1_CLK, SPI1_CLK_A), + }, + { + PAD_FUNC(SPI2_MI, SPI2_MI_A), + PAD_FUNC_GPIO(SPI2_CSB), + PAD_FUNC(SPI2_MO, SPI2_MO_A), + PAD_FUNC(SPI2_CK, SPI2_CLK_A), + }, + { + PAD_FUNC(SPI3_MI, SPI3_MI), + PAD_FUNC_GPIO(SPI3_CSB), + PAD_FUNC(SPI3_MO, SPI3_MO), + PAD_FUNC(SPI3_CLK, SPI3_CLK), + }, + { + PAD_FUNC(EINT13, SPI4_MI_A), + PAD_FUNC_GPIO(EINT11), + PAD_FUNC(EINT12, SPI4_MO_A), + PAD_FUNC(EINT10, SPI4_CLK_A), + }, + { + PAD_FUNC(SPI5_MI, SPI5_MI), + PAD_FUNC_GPIO(SPI5_CSB), + PAD_FUNC(SPI5_MO, SPI5_MO), + PAD_FUNC(SPI5_CLK, SPI5_CLK), + }, +}; + +static const struct pad_func pad1_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(EINT3, SPI0_MI_B), + PAD_FUNC_GPIO(EINT1), + PAD_FUNC(EINT2, SPI0_MO_B), + PAD_FUNC(EINT0, SPI0_CLK_B), + }, + { + PAD_FUNC(EINT9, SPI1_MI_B), + PAD_FUNC_GPIO(EINT7), + PAD_FUNC(EINT8, SPI1_MO_B), + PAD_FUNC(EINT6, SPI1_CLK_B), + }, + { + PAD_FUNC(CAM_PDN1, SPI2_MI_B), + PAD_FUNC_GPIO(CAM_PDN0), + PAD_FUNC(CAM_RST0, SPI2_MO_B), + PAD_FUNC(EINT18, SPI2_CLK_B), + }, + { + }, + { + PAD_FUNC(I2S2_DI, SPI4_MI_B), + PAD_FUNC_GPIO(I2S2_BCK), + PAD_FUNC(I2S2_LRCK, SPI4_MO_B), + PAD_FUNC(I2S2_MCK, SPI4_CLK_B), + }, + { + }, +}; static const struct pad_func nor_pinmux[SPI_NOR_GPIO_SET_NUM][4] = { /* GPIO 36 ~ 39 */ @@ -49,6 +148,22 @@ } } +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + const struct pad_func *ptr; + + if (pad_select == SPI_PAD0_MASK) { + ptr = pad0_funcs[bus]; + } else { + assert((bus == 0 || bus == 1 || bus == 2 || bus == 4) && + pad_select == SPI_PAD1_MASK); + ptr = pad1_funcs[bus]; + } + for (int i = 0; i < 4; i++) + gpio_set_mode(ptr[i].gpio, ptr[i].func); +} + static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, @@ -56,6 +171,11 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, + { .ctrlr = &spi_flash_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Gerrit-Change-Number: 58966 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: majolica: Add spaces for EC firmware to enable Type-C adaptor
by Paul Menzel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59010 ) Change subject: majolica: Add spaces for EC firmware to enable Type-C adaptor ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59010/comment/a4a912e8_6e95e3c8 PS1, Line 7: majolica Please use the common prefixes: mb/amd/majolica. https://review.coreboot.org/c/coreboot/+/59010/comment/6b747cc8_311af527 PS1, Line 7: Add spaces for EC firmware to enable Type-C adaptor FMAP: Increase EC FW space to 148 KB for Type-C adaptor File src/mainboard/amd/majolica/Kconfig: https://review.coreboot.org/c/coreboot/+/59010/comment/38bb4f47_06701dfc PS1, Line 41: 20kByte is are -- To view, visit https://review.coreboot.org/c/coreboot/+/59010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib311e46c8765f17a1af5bc0b00c387268f4cfae5 Gerrit-Change-Number: 59010 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:28:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021