coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
by Frank Chu (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Henry Sun, Marco Chen, Zhuohao Lee, Karthik Ramasubramanian. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/dedede/variants/galtic/variant.c: https://review.coreboot.org/c/coreboot/+/58734/comment/67e3cb25_81d8560c PS5, Line 32: "wifi_sar-galith.hex" > As my understanding, yes. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Gerrit-Change-Number: 58734 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Marco Chen <marcochen(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:26:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add SPI driver support
by Rex-BC Chen (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58966 ) Change subject: soc/mediatek/mt8186: Add SPI driver support ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: @hung-te, I think this patch can be merged? Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/58966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Gerrit-Change-Number: 58966 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:22:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: add apusys init flow
by Paul Menzel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: flora.fu(a)mediatek.com. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58794 ) Change subject: soc/mediatek/mt8195: add apusys init flow ...................................................................... Patch Set 3: (5 comments) Patchset: PS3: It’d be great, if you sent a followup. File src/soc/mediatek/mt8195/apusys.c: https://review.coreboot.org/c/coreboot/+/58794/comment/d9cce33c_0218b015 PS2, Line 13: int i; `unsigned int` or `size_t` https://review.coreboot.org/c/coreboot/+/58794/comment/364c0659_527071b8 PS2, Line 16: printk(BIOS_INFO, "APU_MBOX %p = %#x\n", Why is this level info? https://review.coreboot.org/c/coreboot/+/58794/comment/a7c460df_e98f4497 PS2, Line 24: int i; Ditto. https://review.coreboot.org/c/coreboot/+/58794/comment/a7e9aa7e_6c721082 PS2, Line 26: Setup Set up -- To view, visit https://review.coreboot.org/c/coreboot/+/58794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Gerrit-Change-Number: 58794 Gerrit-PatchSet: 3 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:22:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by Paul Menzel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, flora.fu(a)mediatek.com. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58969 ) Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58969/comment/3a257007_5ddc826f PS2, Line 9: setup set up https://review.coreboot.org/c/coreboot/+/58969/comment/e32131dd_0f5bbdf0 PS2, Line 9: Add APU device apc driver and setup permissions. Please elaborate, what the APU device is, and what kind of permissions you mean. https://review.coreboot.org/c/coreboot/+/58969/comment/51f645d1_d389e810 PS2, Line 13: TEST=boot cherry correctly Please paste the new debug messages, added by the code. File src/soc/mediatek/mt8195/apusys_devapc.c: https://review.coreboot.org/c/coreboot/+/58969/comment/38c60f51_2ddf1682 PS2, Line 212: u32 d, i; Please use native types, for example, `size_t` or `unsigned int`, for count variables. File src/soc/mediatek/mt8195/devapc.c: https://review.coreboot.org/c/coreboot/+/58969/comment/ca90f884_52a2d381 PS2, Line 1889: Setup Set up -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 2 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:20:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01
by Ronak Kanabar (Code Review) 08 Nov '21

08 Nov '21

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59013 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 ...................................................................... vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 The headers added are generated as per FSP v2422_01. Previous FSP version was v2374_01. Changes Include: - Add CnviDdrRfim UPD in FspmUpd.h - UPDs description update in FspmUpd.h BRANCH=None TEST=Build and boot brya Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h 1 file changed, 28 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/59013/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 9e1a414..271e01c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -454,10 +454,10 @@ UINT8 ApertureSize; /** Offset 0x01D0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC - DDR5, 5=ULT/ULX/Mobile Halo Type3, 6=ULT/ULX/Mobile Halo Type4, 8=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 2:Desktop 2DPC DDR5, 5:ULT/ULX/Mobile Halo - Type3, 6:ULT/ULX/Mobile Halo Type4, 8:UP Server + MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server + 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server **/ UINT8 UserBd; @@ -474,7 +474,7 @@ /** Offset 0x01D4 - SA GV System Agent dynamic frequency support and when enabled memory will be training - at three different frequencies. + at four different frequencies. 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled **/ UINT8 SaGv; @@ -1966,9 +1966,11 @@ **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x080D - Reserved +/** Offset 0x080D - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS **/ - UINT8 Reserved27; + UINT8 CnviDdrRfim; /** Offset 0x080E - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1991,7 +1993,7 @@ /** Offset 0x0811 - Reserved **/ - UINT8 Reserved28[3]; + UINT8 Reserved27[3]; /** Offset 0x0814 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -2019,7 +2021,7 @@ /** Offset 0x081B - Reserved **/ - UINT8 Reserved29; + UINT8 Reserved28; /** Offset 0x081C - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -2339,7 +2341,7 @@ /** Offset 0x0854 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x0855 - Extern Therm Status Enables/Disable Extern Therm Status @@ -2379,7 +2381,7 @@ /** Offset 0x085B - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x085C - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2485,7 +2487,7 @@ /** Offset 0x086D - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved31[2]; /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -2544,7 +2546,7 @@ /** Offset 0x087E - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved32; /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) @@ -2754,7 +2756,7 @@ /** Offset 0x08A8 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x08AA - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2786,7 +2788,7 @@ /** Offset 0x08AF - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved34; /** Offset 0x08B0 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -2860,7 +2862,7 @@ /** Offset 0x08BB - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35; /** Offset 0x08BC - Post Code Output Port This option configures Post Code Output Port @@ -2887,7 +2889,7 @@ /** Offset 0x08C1 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved36[3]; /** Offset 0x08C4 - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No @@ -2937,7 +2939,7 @@ /** Offset 0x08DB - Reserved **/ - UINT8 Reserved38[3]; + UINT8 Reserved37[3]; /** Offset 0x08DE - REFRESH_PANIC_WM DEPRECATED @@ -2963,7 +2965,7 @@ /** Offset 0x08E2 - Reserved **/ - UINT8 Reserved39[9]; + UINT8 Reserved38[9]; /** Offset 0x08EB - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2986,7 +2988,7 @@ /** Offset 0x08EE - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved39; /** Offset 0x08EF - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -3003,7 +3005,7 @@ /** Offset 0x08F1 - Reserved **/ - UINT8 Reserved41[3]; + UINT8 Reserved40[3]; /** Offset 0x08F4 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3017,7 +3019,7 @@ /** Offset 0x08F9 - Reserved **/ - UINT8 Reserved42[95]; + UINT8 Reserved41[95]; /** Offset 0x0958 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -3033,7 +3035,7 @@ /** Offset 0x095C - Reserved **/ - UINT8 Reserved43[12]; + UINT8 Reserved42[12]; /** Offset 0x0968 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -3099,7 +3101,7 @@ /** Offset 0x0972 - Reserved **/ - UINT8 Reserved44[2]; + UINT8 Reserved43[2]; /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs @@ -3136,7 +3138,7 @@ /** Offset 0x0A97 - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved44; /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT Select RX pin muxing for SerialIo UART used for debug @@ -3162,7 +3164,7 @@ /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved46[104]; + UINT8 Reserved45[104]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/59013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Gerrit-Change-Number: 59013 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya/var/redrix: Hook up two missing sensors
by Paul Menzel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Chen Wisley, Wisley Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58970 ) Change subject: mb/google/brya/var/redrix: Hook up two missing sensors ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Gerrit-Change-Number: 58970 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:16:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/nvidia,qualcomm: Fix indirect includes
by Paul Menzel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Julius Werner, Kyösti Mälkki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58949 ) Change subject: soc/nvidia,qualcomm: Fix indirect includes ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94 Gerrit-Change-Number: 58949 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:16:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/felwinter: Update typeC EC mux port
by EricR Lai (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59012 ) Change subject: mb/google/brya/var/felwinter: Update typeC EC mux port ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: It better fix in the conn.c -- To view, visit https://review.coreboot.org/c/coreboot/+/59012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Gerrit-Change-Number: 59012 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/felwinter: Update typeC EC mux port
by EricR Lai (Code Review) 08 Nov '21

08 Nov '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59012 ) Change subject: mb/google/brya/var/felwinter: Update typeC EC mux port ...................................................................... mb/google/brya/var/felwinter: Update typeC EC mux port We need to put USB setting in mux order. BUG=b:204230406 TEST=Type C mux configuration is correct. Wrong: added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Correct: added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/59012/1 diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 9bd7ab5..2c4f6f7 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -133,15 +133,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" - device generic 1 alias conn1 on end - end - chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "3" device generic 2 alias conn2 on end end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + device generic 1 alias conn1 on end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/59012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Gerrit-Change-Number: 59012 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
by Paul Menzel (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Subrata Banik, Nick Vaccaro, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58811 ) Change subject: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods" ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58811/comment/199f3fc3_c0c4b16f PS1, Line 11: Reason for revert: Please remove the trailing space. https://review.coreboot.org/c/coreboot/+/58811/comment/4552468b_9239f50c PS1, Line 12: version(x.y.22) Please add exactly one space before the (. https://review.coreboot.org/c/coreboot/+/58811/comment/1e8d18e0_d2ae5d3c PS1, Line 12: doesn't don’t https://review.coreboot.org/c/coreboot/+/58811/comment/eedc0c91_61af104b PS1, Line 13: requires requiring -- To view, visit https://review.coreboot.org/c/coreboot/+/58811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf Gerrit-Change-Number: 58811 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 08:14:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021