coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/kukui: Add new config 'pico6' in coreboot
by Lucas Chen (Code Review) 08 Nov '21

08 Nov '21

Lucas Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58885 ) Change subject: mb/google/kukui: Add new config 'pico6' in coreboot ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9413146913a38ed6a016b6b23ebd6c23040f4469 Gerrit-Change-Number: 58885 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/adl: Drop SGPM, RGPM and EGPM methods
by Maulik V Vaghela (Code Review) 08 Nov '21

08 Nov '21

Maulik V Vaghela has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/57209 ) Change subject: soc/intel/adl: Drop SGPM, RGPM and EGPM methods ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/57209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c7b67b5414d8c80775ab7678ce7b12181af7882 Gerrit-Change-Number: 57209 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
by Maulik V Vaghela (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Subrata Banik, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Subrata Banik, Nick Vaccaro, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58811 to review the following change. Change subject: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods" ...................................................................... Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods" This reverts commit 1399442289607acc5203fb12df64e9081b3c3aa4. Reason for revert: Some Cr50 chips with old firmware version(x.y.22) doesn't support long pulse interrupt command, requires dynamic GPIO PM to be disabled to intercept short pulse interrupt. Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods to support power gating of GPIO communities from the kernel when dynamic GPIO PM is disabled. Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf --- M src/soc/intel/alderlake/acpi/gpio.asl 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/58811/1 diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl index 6a1ba00..376afab 100644 --- a/src/soc/intel/alderlake/acpi/gpio.asl +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -137,3 +137,44 @@ Return (Local0) } + +/* GPIO Power Management bits */ +Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0, 0}) + +/* + * Save GPIO Power Management bits + */ +Method (SGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + Local1 = GPID (Local0) + GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG) + } +} + +/* + * Restore GPIO Power Management bits + */ +Method (RGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, DerefOf(GPMB[Local0])) + } +} + +/* + * Save current setting of GPIO Power Management bits and + * enable all Power Management bits for all communities + */ +Method (EGPM, 0, Serialized) +{ + /* Save current setting and will restore it when resuming */ + SGPM () + /* Enable PM bits */ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf Gerrit-Change-Number: 58811 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google,intel: Split chromeos.c files
by build bot (Jenkins) (Code Review) 08 Nov '21

08 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/stout/bootmode.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132569): https://review.coreboot.org/c/coreboot/+/59011/comment/1129e9e9_2a199221 PS1, Line 44: printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 07:52:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Hook up two missing sensors
by Wisley Chen (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Chen Wisley, Paul Menzel. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58970 ) Change subject: mb/google/brya/var/redrix: Hook up two missing sensors ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58970/comment/09aa6d09_a384d18b PS1, Line 7: mb/google/brya/var/redrix: Add two thermal sensor setting > 1. Add thermal sensors for SOC and voltage regulator […] Done File src/mainboard/google/brya/variants/redrix/overridetree.cb: https://review.coreboot.org/c/coreboot/+/58970/comment/1ceba6d7_6ed52eaf PS1, Line 88: register "options.tsr[2].desc" = ""Charger"" > So, the charger sensor was incorrect before? yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/58970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Gerrit-Change-Number: 58970 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 08 Nov 2021 07:51:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google,intel: Split chromeos.c files
by Kyösti Mälkki (Code Review) 08 Nov '21

08 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: mb/google,intel: Split chromeos.c files ...................................................................... mb/google,intel: Split chromeos.c files Move all the low-level GPIO support in bootmode.c files and build them for all stages. Keep ChromeOS related ACPI and lbtable support in chromeos.c files and build them only for ramstage. Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/Makefile.inc A src/mainboard/google/auron/bootmode.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/Makefile.inc A src/mainboard/google/beltino/bootmode.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/Makefile.inc A src/mainboard/google/butterfly/bootmode.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/jecht/Makefile.inc A src/mainboard/google/jecht/bootmode.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/link/Makefile.inc A src/mainboard/google/link/bootmode.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/Makefile.inc A src/mainboard/google/parrot/bootmode.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/slippy/Makefile.inc A src/mainboard/google/slippy/bootmode.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/Makefile.inc A src/mainboard/google/stout/bootmode.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/Makefile.inc A src/mainboard/intel/baskingridge/bootmode.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/Makefile.inc A src/mainboard/intel/emeraldlake2/bootmode.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/strago/Makefile.inc A src/mainboard/intel/strago/bootmode.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/samsung/lumpy/Makefile.inc A src/mainboard/samsung/lumpy/bootmode.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/Makefile.inc A src/mainboard/samsung/stumpy/bootmode.c M src/mainboard/samsung/stumpy/chromeos.c 39 files changed, 350 insertions(+), 278 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59011/1 diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index f642243..0ce9ace 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -2,9 +2,8 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_HAVE_SPD_IN_CBFS) += spd.c diff --git a/src/mainboard/google/auron/bootmode.c b/src/mainboard/google/auron/bootmode.c new file mode 100644 index 0000000..268ff42 --- /dev/null +++ b/src/mainboard/google/auron/bootmode.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +#include "onboard.h" + +int get_write_protect_state(void) +{ + return get_gpio(CROS_WP_GPIO); +} + diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 6872ec9..a4c8c0c 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -19,11 +19,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(CROS_WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 77edc30..c1ea38b 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -2,9 +2,8 @@ bootblock-y += bootblock.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-y += chromeos.c ramstage-y += lan.c smm-y += variants/$(VARIANT_DIR)/led.c diff --git a/src/mainboard/google/beltino/bootmode.c b/src/mainboard/google/beltino/bootmode.c new file mode 100644 index 0000000..b85588e --- /dev/null +++ b/src/mainboard/google/beltino/bootmode.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/common/gpio.h> + +#include "onboard.h" + +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +void init_bootmode_straps(void) +{ + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); +} + diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 325a265..44e361c 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -20,21 +20,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -void init_bootmode_straps(void) -{ - stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 33a97f5..ecd5cc0 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -2,8 +2,8 @@ ramstage-y += ec.c -romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/butterfly/bootmode.c b/src/mainboard/google/butterfly/bootmode.c new file mode 100644 index 0000000..d5a44a1 --- /dev/null +++ b/src/mainboard/google/butterfly/bootmode.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <ec/quanta/ene_kb3940q/ec.h> +#include "ec.h" +#include "onboard.h" + +int get_write_protect_state(void) +{ + return !get_gpio(WP_GPIO); +} + +int get_lid_switch(void) +{ + return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; +} + +/* FIXME: VBOOT reads this in ENV_ROMSTAGE. */ +int get_recovery_mode_switch(void) +{ + if (ENV_RAMSTAGE) + return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO); + + return 0; +} + +bool mainboard_ec_running_ro(void) +{ + // TODO: MLR + // The firmware read/write status is a "virtual" switch and + // will be handled elsewhere. Until then hard-code to + // read/write instead of read-only for developer mode. + return false; +} diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 84f04be..7b37568 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -6,9 +6,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <ec/quanta/ene_kb3940q/ec.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" #include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) @@ -28,34 +26,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !get_gpio(WP_GPIO); -} - -int get_lid_switch(void) -{ - return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; -} - -/* FIXME: VBOOT reads this in ENV_ROMSTAGE. */ -int get_recovery_mode_switch(void) -{ - if (ENV_RAMSTAGE) - return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO); - - return 0; -} - -bool mainboard_ec_running_ro(void) -{ - // TODO: MLR - // The firmware read/write status is a "virtual" switch and - // will be handled elsewhere. Until then hard-code to - // read/write instead of read-only for developer mode. - return false; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index ed74d75..5f8aea2 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -1,9 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c smm-y += led.c diff --git a/src/mainboard/google/jecht/bootmode.c b/src/mainboard/google/jecht/bootmode.c new file mode 100644 index 0000000..99fc54e --- /dev/null +++ b/src/mainboard/google/jecht/bootmode.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +#include "onboard.h" + +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +void init_bootmode_straps(void) +{ + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); +} diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 66a0523..de53a6b 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -6,6 +6,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> + #include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) @@ -20,21 +21,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -void init_bootmode_straps(void) -{ - stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 6b3f1b5..ba7e0fd 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -2,8 +2,8 @@ ramstage-y += ec.c -romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads # Order of names in SPD_SOURCES is important! diff --git a/src/mainboard/google/link/bootmode.c b/src/mainboard/google/link/bootmode.c new file mode 100644 index 0000000..e543a15 --- /dev/null +++ b/src/mainboard/google/link/bootmode.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +int get_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index d83fbce..82a132f 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -25,11 +25,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index f2166e1..ecd5cc0 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -2,7 +2,7 @@ ramstage-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/parrot/bootmode.c b/src/mainboard/google/parrot/bootmode.c new file mode 100644 index 0000000..b7e101a --- /dev/null +++ b/src/mainboard/google/parrot/bootmode.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +#include "onboard.h" + +int get_lid_switch(void) +{ + return get_gpio(GPIO_LID); +} + +int get_write_protect_state(void) +{ + return !get_gpio(GPIO_SPI_WP); +} + +int get_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +bool mainboard_ec_running_ro(void) +{ + return get_recovery_mode_switch(); +} diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 2789d38..9438b4f 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> @@ -32,26 +31,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_lid_switch(void) -{ - return get_gpio(GPIO_LID); -} - -int get_write_protect_state(void) -{ - return !get_gpio(GPIO_SPI_WP); -} - -int get_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -bool mainboard_ec_running_ro(void) -{ - return get_recovery_mode_switch(); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 2a2541d..f1f7023 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -2,7 +2,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/slippy/bootmode.c b/src/mainboard/google/slippy/bootmode.c new file mode 100644 index 0000000..3a37bbd --- /dev/null +++ b/src/mainboard/google/slippy/bootmode.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h> + +int get_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 829c8b8..a198dbb 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -18,11 +18,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index a773a2d..a61691f 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -2,8 +2,8 @@ ramstage-y += ec.c -romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c smm-y += ec.c diff --git a/src/mainboard/google/stout/bootmode.c b/src/mainboard/google/stout/bootmode.c new file mode 100644 index 0000000..37c0918 --- /dev/null +++ b/src/mainboard/google/stout/bootmode.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <device/device.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include "ec.h" +#include <ec/quanta/it8518/ec.h> + +int get_write_protect_state(void) +{ + return !get_gpio(GPIO_SPI_WP); +} + +int get_lid_switch(void) +{ + /* hard-code to open */ + return 1; +} + +/* + * The recovery-switch is virtual on Stout and is handled via the EC. + * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC + * indicated the recovery keys were pressed. We use a global flag for + * rec_mode to be used after RTC_POWER_STS has been cleared. + * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW. + */ +int get_recovery_mode_switch(void) +{ + static int ec_in_rec_mode; + static int ec_rec_flag_good; + + if (ec_rec_flag_good) + return ec_in_rec_mode; + + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); + + u8 ec_status = ec_read(EC_STATUS_REG); + + printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", + __func__, ec_status, reg8 & RTC_BATTERY_DEAD); + + ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && + ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); + ec_rec_flag_good = 1; + return ec_in_rec_mode; +} + +bool mainboard_ec_running_ro(void) +{ + return !!get_recovery_mode_switch(); +} + diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index f2b880c..b43e9fa 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -3,15 +3,9 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/device.h> - #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" -#include <ec/quanta/it8518/ec.h> #include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) @@ -34,51 +28,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !get_gpio(GPIO_SPI_WP); -} - -int get_lid_switch(void) -{ - /* hard-code to open */ - return 1; -} - -/* - * The recovery-switch is virtual on Stout and is handled via the EC. - * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC - * indicated the recovery keys were pressed. We use a global flag for - * rec_mode to be used after RTC_POWER_STS has been cleared. - * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW. - */ -int get_recovery_mode_switch(void) -{ - static int ec_in_rec_mode; - static int ec_rec_flag_good; - - if (ec_rec_flag_good) - return ec_in_rec_mode; - - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); - - u8 ec_status = ec_read(EC_STATUS_REG); - - printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", - __func__, ec_status, reg8 & RTC_BATTERY_DEAD); - - ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && - ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); - ec_rec_flag_good = 1; - return ec_in_rec_mode; -} - -bool mainboard_ec_running_ro(void) -{ - return !!get_recovery_mode_switch(); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index c69f7c8..0eec3d3 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -2,6 +2,5 @@ romstage-y += gpio.c -romstage-y += chromeos.c -ramstage-y += chromeos.c -verstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/intel/baskingridge/bootmode.c b/src/mainboard/intel/baskingridge/bootmode.c new file mode 100644 index 0000000..9e09695 --- /dev/null +++ b/src/mainboard/intel/baskingridge/bootmode.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h> + +int get_recovery_mode_switch(void) +{ + /* + * Recovery: GPIO69, Connected to J8E3, however the silkscreen says + * J8E2. The jump is active high. + */ + return get_gpio(GPIO_REC_MODE); +} + +int get_write_protect_state(void) +{ + /* Write protect is active low, so invert it here */ + return !get_gpio(GPIO_SPI_WP); +} + diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index a926325..9af0f8f 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -3,8 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" @@ -26,21 +24,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_recovery_mode_switch(void) -{ - /* - * Recovery: GPIO69, Connected to J8E3, however the silkscreen says - * J8E2. The jump is active high. - */ - return get_gpio(GPIO_REC_MODE); -} - -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !get_gpio(GPIO_SPI_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index 151a3c3..a299ca6 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c diff --git a/src/mainboard/intel/emeraldlake2/bootmode.c b/src/mainboard/intel/emeraldlake2/bootmode.c new file mode 100644 index 0000000..75c1db6 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/bootmode.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +int get_recovery_mode_switch(void) +{ + /* Recovery: GPIO22, active low */ + return !get_gpio(GPIO_REC_MODE); +} + +int get_write_protect_state(void) +{ + /* Write protect is active low, so invert it here */ + return !get_gpio(GPIO_SPI_WP); +} + diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 3e17e8e..dd7a643 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -3,8 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" @@ -26,18 +24,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_recovery_mode_switch(void) -{ - /* Recovery: GPIO22, active low */ - return !get_gpio(GPIO_REC_MODE); -} - -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !get_gpio(GPIO_SPI_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 004a6a2..5a91ce9 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -2,8 +2,8 @@ bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += gpio.c diff --git a/src/mainboard/intel/strago/bootmode.c b/src/mainboard/intel/strago/bootmode.c new file mode 100644 index 0000000..7775419 --- /dev/null +++ b/src/mainboard/intel/strago/bootmode.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> + +#include "onboard.h" + +int get_write_protect_state(void) +{ + /* + * This function might get queried early in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. + * Configuring this GPIO as input so that there isn't any ambiguity + * in the reading. + */ + if (ENV_ROMSTAGE_OR_BEFORE) + gpio_input_pullup(WP_GPIO); + + /* WP is enabled when the pin is reading high. */ + return !!gpio_get(WP_GPIO); +} + diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index e516a60..71918cf 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -18,21 +18,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* - * This function might get queried early in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. - * Configuring this GPIO as input so that there isn't any ambiguity - * in the reading. - */ - if (ENV_ROMSTAGE_OR_BEFORE) - gpio_input_pullup(WP_GPIO); - - /* WP is enabled when the pin is reading high. */ - return !!gpio_get(WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 1fd9498..7ee0daa 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -2,8 +2,8 @@ ramstage-y += ec.c -romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/samsung/lumpy/bootmode.c b/src/mainboard/samsung/lumpy/bootmode.c new file mode 100644 index 0000000..ea777b5 --- /dev/null +++ b/src/mainboard/samsung/lumpy/bootmode.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <device/pci_ops.h> +#include <ec/smsc/mec1308/ec.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include "ec.h" +#include "onboard.h" + +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +void init_bootmode_straps(void) +{ + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); +} + +int get_lid_switch(void) +{ + return ec_read(0x83) & 1; +} + +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + +bool mainboard_ec_running_ro(void) +{ + return !ec_read(0xcb); +} diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index d9db159..5fa2e63 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -3,16 +3,11 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/pci_ops.h> -#include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" -#include "ec.h" -#include <ec/smsc/mec1308/ec.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -32,38 +27,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -int get_lid_switch(void) -{ - return ec_read(0x83) & 1; -} - -int get_power_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - return (gen_pmcon_1 >> 9) & 1; -} - -void init_bootmode_straps(void) -{ - stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); -} - -bool mainboard_ec_running_ro(void) -{ - return !ec_read(0xcb); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index 57ec1c5..9d5e5b4 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/samsung/stumpy/bootmode.c b/src/mainboard/samsung/stumpy/bootmode.c new file mode 100644 index 0000000..7aeb1d7 --- /dev/null +++ b/src/mainboard/samsung/stumpy/bootmode.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <device/pci_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +#include "onboard.h" + +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + +void init_bootmode_straps(void) +{ + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); +} diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index dd5ded2..990ec95 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -3,8 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/pci_ops.h> -#include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -30,28 +28,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -int get_power_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - return (gen_pmcon_1 >> 9) & 1; -} - -void init_bootmode_straps(void) -{ - stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS recovery feature
by build bot (Jenkins) (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57131 ) Change subject: amdfwtool: Add support for AMD's BIOS recovery feature ...................................................................... Patch Set 30: (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132564): https://review.coreboot.org/c/coreboot/+/57131/comment/29604f78_231b32c7 PS30, Line 1846: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/57131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Gerrit-Change-Number: 57131 Gerrit-PatchSet: 30 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Mon, 08 Nov 2021 07:42:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by Yu-Ping Wu (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, flora.fu(a)mediatek.com. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58969 ) Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... Patch Set 2: (19 comments) File src/soc/mediatek/mt8195/apusys_devapc.c: https://review.coreboot.org/c/coreboot/+/58969/comment/5920c684_bab534e4 PS2, Line 58: APUSYS_NOC_DAPC_AO Lower case name. https://review.coreboot.org/c/coreboot/+/58969/comment/43af17bd_d8c02738 PS2, Line 78: APUSYS_AO_Devices Lower case name. https://review.coreboot.org/c/coreboot/+/58969/comment/7eedbd80_f7e4f820 PS2, Line 166: _Static_assert(ARRAY_SIZE(APUSYS_AO_Devices) == 71); https://review.coreboot.org/c/coreboot/+/58969/comment/a670c2e6_f878d921 PS2, Line 179: 0x%x %#x Same for all occurrences in this file. https://review.coreboot.org/c/coreboot/+/58969/comment/994dac5a_45e8e017 PS2, Line 181: ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; : goto exit; return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; https://review.coreboot.org/c/coreboot/+/58969/comment/f7358998_ef338d60 PS2, Line 191: if (slave < APUSYS_NOC_DAPC_AO_SLAVE_NUM && : domain_id < APUSYS_NOC_DAPC_AO_DOM_NUM) { : base = (u32 *)((size_t)APUSYS_NOC_DAPC_AO_BASE + : domain_id * 0x40 + apc_register_index * 4); : apuapc_writel(apuapc_readl(base) & clr_bit, base); : apuapc_writel(apuapc_readl(base) | set_bit, base); : ret = APUSYS_APC_OK; : } else { : printk(BIOS_DEBUG, "[NOC_DAPC] %s: %s, %s:0x%x, %s:0x%x\n", : __func__, "out of boundary", "slave", slave, "domain_id", : domain_id); : ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; : } Rewrite as if (slave >= APUSYS_NOC_DAPC_AO_SLAVE_NUM) { printk(BIOS_ERR, "[NOC_DAPC] %s: slave out of boundary: %#x", __func__, slave); return APUSYS_APC_ERR_OUT_OF_BOUNDARY; } if (domain_id >= ...) { ... } base = ...; ...; return APUSYS_APC_OK; https://review.coreboot.org/c/coreboot/+/58969/comment/911e8f13_47c5c2c1 PS2, Line 205: exit: : return ret; Remove https://review.coreboot.org/c/coreboot/+/58969/comment/8e8a6404_77c2b16e PS2, Line 217: <= Why is this "<=" instead of "<"? Should we define reg_num as DIV_ROUND_UP(APUSYS_NOC_DAPC_AO_SLAVE_NUM, APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM) https://review.coreboot.org/c/coreboot/+/58969/comment/c5f5ef78_8cccc5bd PS2, Line 231: = NULL No need to initialize. https://review.coreboot.org/c/coreboot/+/58969/comment/70d8c67e_72260ba8 PS2, Line 239: ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; : goto exit; return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED https://review.coreboot.org/c/coreboot/+/58969/comment/90e84300_045098e3 PS2, Line 249: if (slave < APUSYS_APC_SYS0_AO_SLAVE_NUM && : domain_id < APUSYS_APC_SYS0_AO_DOM_NUM) { : base = (u32 *)((size_t)APUSYS_APC_AO_BASE + domain_id * 0x40 + : apc_register_index * 4); : apuapc_writel(apuapc_readl(base) & clr_bit, base); : apuapc_writel(apuapc_readl(base) | set_bit, base); : ret = APUSYS_APC_OK; : } else { : printk(BIOS_DEBUG, "[APUAPC] %s: %s, %s:0x%x, %s:0x%x\n", : __func__, "out of boundary", "slave", slave, "domain_id", : domain_id); : ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; : } : : exit: : return ret; Same as set_slave_noc_dapc(). Please rewrite. https://review.coreboot.org/c/coreboot/+/58969/comment/fd0426bc_00557430 PS2, Line 275: <= Same. https://review.coreboot.org/c/coreboot/+/58969/comment/6fd9db52_baa7ecda PS2, Line 377: set_bit Write the value inline: BIT(APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER) | BIT(APUSYS_APC_SYS0_LOCK_BIT_DEVAPC_AO_WRAPPER) File src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h: https://review.coreboot.org/c/coreboot/+/58969/comment/21319240_9a454922 PS2, Line 10: APUSYS_APC_ERR_STATUS Lower case name. https://review.coreboot.org/c/coreboot/+/58969/comment/08094c62_0dce2396 PS2, Line 13: 0x1000 Why use 0x1000 instead of 1 for errors? Are these values copied from somewhere? https://review.coreboot.org/c/coreboot/+/58969/comment/c8066729_0bed65e3 PS2, Line 23: APUSYS_APC_PERM_TYPE Lower case name. https://review.coreboot.org/c/coreboot/+/58969/comment/c7a4b166_158419e4 PS2, Line 31: APUSYS_APC_DOMAIN_ID Lower case name. https://review.coreboot.org/c/coreboot/+/58969/comment/899ee89d_5c5b578b PS2, Line 50: APC_DOM_16 Lower case name. https://review.coreboot.org/c/coreboot/+/58969/comment/7b641ad4_8023a3b2 PS2, Line 51: unsigned char d0_permission; : unsigned char d1_permission; : unsigned char d2_permission; : unsigned char d3_permission; : unsigned char d4_permission; : unsigned char d5_permission; : unsigned char d6_permission; : unsigned char d7_permission; : unsigned char d8_permission; : unsigned char d9_permission; : unsigned char d10_permission; : unsigned char d11_permission; : unsigned char d12_permission; : unsigned char d13_permission; : unsigned char d14_permission; : unsigned char d15_permission; Why not use an array? unsigned char d_permission[16]; -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 2 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 07:27:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS A/B recovery feature
by Bao Zheng (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56773 ) Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature ...................................................................... Patch Set 30: (4 comments) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/56773/comment/a8ec1aa6_c11b48d0 PS29, Line 769: pspdir2 > pspdir2 != NULL Done https://review.coreboot.org/c/coreboot/+/56773/comment/908bfb5f_a848b2bf PS29, Line 775: pspdir2 > same. Done https://review.coreboot.org/c/coreboot/+/56773/comment/1d9474cd_32baadb5 PS29, Line 792: uint8_t > fw_type type Done https://review.coreboot.org/c/coreboot/+/56773/comment/b35c9467_34371018 PS29, Line 796: type > (uint8_t)type Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Gerrit-Change-Number: 56773 Gerrit-PatchSet: 30 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Nov 2021 07:27:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Pack out-of-bounds check into a function and move
by Bao Zheng (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Martin Roth, Marshall Dawson, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58764 ) Change subject: amdfwtool: Pack out-of-bounds check into a function and move ...................................................................... Patch Set 4: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/58764/comment/24c88a0d_3c23e3f1 PS3, Line 738: if (count > MAX_PSP_ENTRIES) { > But in assert_fw_entry, the comparison is change to ">=". I assume the effect are the same. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Gerrit-Change-Number: 58764 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Mon, 08 Nov 2021 07:27:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021